Sharp MZ-3500 service manual A7 A6 A5A4A3A2AlAO H E X Uhus 1 O, 1 1 1 1 0 KI1 Dl Do 17 D6 D5, Sttl

M 7.3500

MAIN CPU

I/O PORT IN MEMORY MAPPER

A D D K K SS

A7 A6 A5A4A3A2AlAO H E X UHUS 1 O

01

r\i IT

DO

D7

11 1 1 1 1 0 KI)1 Dl

DO 1)7 D6 D5

D4 OUT

D2 Dl

1 1 1 1 1 1 1 0 FE DO D4 D3

D2 INI

Dl

DO

D7

D6

D5

1 1 1 1 1 1 1 1 FF 1)4 I N D3

D2

Dl

DO

D7

D6

SKQB

11

SKI S

M S ]

M S O

M<\3

MA2

M A I

M A O

MO2

M O I

MOO

S W 4

b«3

M\2

Sttl

she

FD3

FD2

H>1

SKDY

SACK

1 N P 2

IMM IN'1'0 M F 2 Mhl

SRQ Bus request from the mam CPU to the sob-CPU

Sub-CPU reset signal

Memory system define

Bank select signal to memory area of COOO-FFFF.

_J

Bank select signal to memory area of 2000-3FFF.

System assign switch

	FD assign
	(SW8)
•f>	Sub-CPU READY signal
•p	Sub-CPU acknowledge signal
	Interrupt status

1.All output signals are reset to low level upon power on, except for SRBQ that goes high.

2.Noted with a star mark "£" are input/output signals, and rest of others are processedin the LSI.

#1 I/O port output of ME1 and ME2 uses the memory at the addresses.

( ME2->8000~BFFF

I ME1->-4000~7FFF

When ME1 and ME2 are in high state. RSAB (RASA) is inhibited during memory addresses in RAM-A that correspond to overlayed addresses for MET and ME2 This is not true during SD1 mode.

	M II	TO t MOI«m			01 iri	T hkoM fMont
Mm	n (iHj 1I 1 H M 2hTisn 1 T4h						1 h
i i -^. t <,	TvfT J i\=TjTNT7			JM3	IM 2	IM 1	M It
							"- T"
					1
"fJ~						X
	1	j X	X		1	L	H
					1	H	I
11 1 H	H 1 H 1				L	H	H
" I "	H	j H	j H		H	I '	1
H j H	H j H j H H				H	L 1 H
i	l		FKOM SI in				TO HA
	""•» M" l"

Wait timing generator

WAIT is issued once per main CPU fetch cycle. Its outut is tri state