Sharp MZ-3500 640 x 400 bits display mode FH = 20.92 kHz FV = 47.3 Hz, Setup of GCD master/slave

Page 31

MZ3500

(2) 640 x 400 bits display mode

fH = 20.92 kHz

fV = 47.3 Hz					X : Y : 1 : 1
					X : Y : 1 : 1
	GDC-1 (80 digits)				GDC-2	graphic)
	Character	display (40 digits)		8 bits			16 bits
Dot clock(OD)	(19 66MHz)			19.66MHz	(50.86ns)		9.83MHz (101 92ns)
Dot clock(OD)	(9 83 MHz)			19.66MHz	(50.86ns)		9.83MHz (101 92ns)
	(9 83 MHz)
2XCCLK	(4.9152MHz)			4.9152MHz	(203.45ns)		24575MHz (406 9ns)
2XCCLK	(2.4575MHz)			4.9152MHz	(203.45ns)		24575MHz (406 9ns)
	(2.4575MHz)
Horizontal display time	32 55^s	80 Chr. /40 Chr.		-			-
				-			-
HFP		4.88fjs		«-			-
HS		4^is					5Chr.
HS		4^is	*~	(tREF=0.6ms)		*~	(tREF = 1.23ms)
			*~	(tREF=0.6ms)		*~	(tREF = 1.23ms)
HBP		6 5ys		-			-
				-
Vertical display time		19.16ms		-			-
				-			-
VFP		0.527ms		-			-
				-
VP		0.24 ms		«-			-
VBP		1.198ms		-			-
				-

Total rasters: 441 rasters

Display rasters 400 rasters

(3)CRT synchronizing signal specification (400 raster CRT)

1.Horizontal synchronization frequency (fH): 20.92kHz

2.Vercial synchronization frequency (fV): 47.3Hz

3.Total rasters: 441 rasters

4.Rasters used: 400 rasters

5.Display dots: 640 x 400 dots

6.Dot clock: (19.66MHz)

7.Timing

9.HS, VS, and VIDEO signals are supplied from the LS type TTL 1C(totem pole)

6)Setup of GCD master/slave

(1)Master/slave setup by combination

	^^•v^^	Character
	^^•\^^ GDC		40 digits	80 digits
	Graphic	^^^^	40 digits	80 digits
	Graphic	^^^^
	GDC	^"\^
	Without VRAM PWB		Character	Character
	8 bit structure
	48K byte		Character	Ch3rai.te'
	200 rasters
	16-bit structure
	96 K byte		Character	Graphic
	48K byte		Character	Graphic
	48K byte

400 rasters

Master should be setup in the abovei.ia.

(2) I/O signal switching

PIT A ft to

(8255.PB7 )

VFP: 11 rasters (0.5ms)

fiQ /I p ,, ,.

,f c

(CSP - 2)

VSYNC

Switching

Circuit

VS- 5 rasters (0.24ms)

!VBP - 25 rasters (1.2ms)

8.Output method HS, VS. and VIDEO are indpendent outputs.

Image 31

Contents Personal Computer Model Z-350 Video TimerBACKUP, INIT, COPY, DEBUG, Killall MemorySFDI/F Refer to the page TIN Circuit DiagramSlot Slot2 LSI, 1C CmosicChange Disp PresetSymbol SdispUser Basic Area RAMBase SystemMZ-1D07 MZ3500 System configuration of Model MS1 = D MSO = 0 L Software Memory ConfigurationTiming of Reset Signal ROM-IPL SD1 System Loading & CP/MFfff Bank SelectMAO ROM SD3 RAM based BasicOperational description BankMain Memory Mapper Block diagram Relation between MMR main memoryThis paragraph discusses main CPU I/O Main CPU and I/O portTable below describes address map Sub CPU and I/O port 0001Main CPU \m MZ3500Coab Memory mapper MMRSP6102R-001 Block diagramTo Reset Address BUSRAS ROW Address Select Line Address Select Signal MZ3500 Memory mapper MMR SP6102R-001 signal descriptionSrdy Pin No RO1B IN/OUTRO2B 1 1 1 1 1 1 FF 14 I N D3 A7 A6 A5A4A3A2AlAO H E X Uhus 1 O1 1 1 1 0 KI1 Dl Do 17 D6 D5 D2 Dl 1 1 1 1 1 0 FE do D4 D3MZ3500 Memory ROMIPL, RAMCOM, S-RAM select circuit CRT SpecificationAsci Summary of video display specificationGraphic dot Dot pitchBlue Dot color designated byKA7 CH ATCH AI +,! AT A r + + G Ascii CG #1 FFFVideo RAM Structure of Vram #07FFA Structure of character Vram When read/write from GDC #0000 8bit Read/write by Z-80 via the GDC 640 x 200 dots display modeFV = 60 Hz 16KO signal switching 640 x 400 bits display mode FH = 20.92 kHz FV = 47.3 HzSetup of GCD master/slave Master/slave setup by combinationGraphic V-RAM Address Crtc block diagramPage Master slice LSI CSP-1 SP6102C 002 signal description » CK CSP-1 Block DiagramCSH HSY2 2BLK2 LSI CSP-2 SP6012C-003 Signal DescriptionCAS OUT CSP 2 Block Diagram3r00 DSP2 OUTGDC Graphic display controller UPD7220 signal description CSR-1MAGE AD15ILC2NK-CLC AT~BTIStructure CG Address Select CircuitCircuit description VsyncBlsc Character Vram select circuitRead/write from the Z-80 to V-RAM Set GDC command codeFifo Empty? Return when all parameters were sentCsrw C 49H -COMMAND Code Write C 23H Command Code Vecte C 6CH Command CodeFollowing manner Dot display program example-1 60HExplanation VECTE. Dot address is structured on the screenP4 88H P5 HH I T E C 23HKind of line solid line Outline Floppy diskTJ ILJ n Ci D ci Ici VnVn n nV nnn7Data MZ3500 MFD interface block diagram 22 «- o Window FDC UPD765UPD765 signal description MFM recording method Trigger motor on of the timer 555 Selects FDDMZ350C Port used in the MFD interface is as followsControl during seek and recalibration Controls during read, write, seek, and re- calibrateMedia detection 3500 Precompensate CircuitPurpose String of data Pulses from the FDD Data window VFO circuitFilter Phase Detector Amplifier Window VFO circuit configurationBQA MFM ModeFM mode timing chart \\\\ Aload Side =3DSC Indicates the byte position From the top of directory 76 iy 7 EH 77 / FFH\128 Track 10 sector1015 Ii PatatB144 6145 B146 B147 39 B148 B149 B150 B151 39 B74 B75Example 7-bits, even parity, 1 stop bit General specificationData transmission format MZS500Start AC controlsOFF KTS MZ3500 Data output control8251 AC RXEN,UTR , T X E N 3SOO128 2009 6.3 256«--N Wl -»8253 OUT 8253DS7 Printer interfacing circuitAA3 DATOutput General description of the parallel interfaceData transfer timing I/O port map DIN Clock circuit SchematicRead Hold Write Hold SETLSB MSB MZ3500 PD1990AC Block diagram» GETE1 J MmmilSFD 1/F 3500S I C GP I/OFD2 SW2 SW1 On on CE332P OFF on MZ1P02 On OFF IO2824 OFF OFFDipswa SEC\f Canbe in either state Functions Block diagramDescription of each block +5V Switching regulatorTiming chart Alarm generation circuitAt rrn Specification of keyboard controlKey Strobe Key search timing2s 2s22 21 Key22.5/-s 132.5Protocol Key to sub CPU Keyboard controller basic flow ALE DBO DB7 GND Keyboard controller signal descriptionXTAL1 XTAL2 Reset INT PINOn OFF Sub-CPU side ProcedureS C I I 00-FF Shared RAMCRT inter face test Abnormal1 5 c * O DR O.7 Abnormal test endingReady O.H ROM-IPL Main CPU Checker Flow Chart 1/2 100 Main CPU Checker Flow Chart M?M7*500 101Keyboard test Keyboard controller ROM testIPL Flow Chart Load Iocs SEEK& Read Jump \ Boot Address SystemSEEK, Read Error Error105 SUB CPU IPL Flow ChartR R R R F1 LJ LJ LJ LJ LJ LJ LJU J l J J L i J L L j l J J L l J L L l LU LU U LJ LlJ LJ U UAIO IwCRoB MZ-35OO Parts Guide LI LED PWB No Parts CodeS C R I P T I O N IE--or Ooss-zw Qcnw MZ-3500Parts Code N T KS C R I P T I O N ConnectorA a N a D MZ-3500NO. Parts Code Parts CodeNEW VH S N 7 4 0 6 NMark Rank Part S C R I P T I O NCoos M2-3500 J9, MZ1K02,1K03,1K04,1K05 Key unitNO. Parts Code SOCLSI RAM LA aD e Tin N a a Parts CodeMZ-3500 Sharp Corporation