Sharp MZ-3500 service manual Software Memory Configuration, MS1 = D MSO = 0 L

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MZ3500

2. SOFTWARE (MEMORY) CONFIGURATION

Memory will be operated under four states of SDO ~ SD3, depending on the hardware and software configurations. In the paragraphs to follow, description will be made for those four states.

	MAIN CPU
MAS	0	0	1
MA2	0	0	1
MAI	0	0	1
MAO	0	1	1
FFFF		V	FFFF T
FFFF

? IRAM(COM^ reoojOO1—— ^\

2-1.SDO (INITIALIZE STATE)

SDO can only exist immediately after power on, and the system executes IPL under this condition and that the system thus loaded will automatically assign memory area

for SD1, SD2. and SD3.

SUB CPU

MS1 = ° (D

MSO = 0 (L)

RAMA RAMA

cooo

BFFF

		\\
	RAMA	u
		\ \
		\\
8000
7FFF		\\
		\\		ROM
		N		ROM
			v	(SPAPE)
			V \
	RAMA			\
4 0 0 0				4 0 0 0
3FFF i				4 0 0 0
ROME [
I		I		27FF
200 0 I	'			RAM (COM) 2 0 0 0
				1 FFF
O F FF				ROM
O F FF	ROM			IPL
				IPL

0 0 0 0	J PL			0 0 0 0
0 0 0 0				0 0 0 0

*7

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Contents Personal Computer Model Z-350 Timer BACKUP, INIT, COPY, DEBUG, KillallMemory VideoRefer to the page TIN Circuit Diagram Slot Slot2LSI, 1C Cmosic SFDI/FPreset SymbolSdisp Change DispBasic Area RAM BaseSystem UserMZ-1D07 MZ3500 System configuration of Model Software Memory Configuration MS1 = D MSO = 0 LTiming of Reset Signal SD1 System Loading & CP/M ROM-IPLMAO Bank SelectFfff SD3 RAM based Basic Operational descriptionBank ROMBlock diagram Relation between MMR main memory Main Memory MapperTable below describes address map Main CPU and I/O portThis paragraph discusses main CPU I/O 0001 Main CPU \mMZ3500 Sub CPU and I/O portMemory mapper MMRSP6102R-001 Block diagram To ResetAddress BUS CoabSrdy MZ3500 Memory mapper MMR SP6102R-001 signal descriptionRAS ROW Address Select Line Address Select Signal Pin No RO2B IN/OUTRO1B A7 A6 A5A4A3A2AlAO H E X Uhus 1 O 1 1 1 1 0 KI1 Dl Do 17 D6 D5D2 Dl 1 1 1 1 1 0 FE do D4 D3 1 1 1 1 1 1 FF 14 I N D3MZ3500 Memory ROMIPL, RAMCOM, S-RAM select circuit Specification CRTSummary of video display specification AsciDot pitch BlueDot color designated by Graphic dotCH AI +,! AT A r + + G CH ATKA7 #1 FFF Ascii CGVideo RAM Structure of Vram #0000 Structure of character Vram When read/write from GDC#07FFA Read/write by Z-80 via the GDC 640 x 200 dots display mode 8bit16K FV = 60 Hz640 x 400 bits display mode FH = 20.92 kHz FV = 47.3 Hz Setup of GCD master/slaveMaster/slave setup by combination O signal switchingCrtc block diagram Graphic V-RAM AddressPage Master slice LSI CSP-1 SP6102C 002 signal description CSH CSP-1 Block Diagram» CK LSI CSP-2 SP6012C-003 Signal Description HSY2 2BLK2CSP 2 Block Diagram 3r00DSP2 OUT CAS OUTGDC Graphic display controller UPD7220 signal description AD15ILC2 NK-CLCAT~BTI CSR-1MAGECG Address Select Circuit StructureVsync Circuit descriptionCharacter Vram select circuit BlscSet GDC command code Read/write from the Z-80 to V-RAMReturn when all parameters were sent Csrw C 49H -COMMAND CodeWrite C 23H Command Code Vecte C 6CH Command Code Fifo Empty?60H ExplanationVECTE. Dot address is structured on the screen Following manner Dot display program example-1Kind of line solid line I T E C 23HP4 88H P5 HH Floppy disk OutlineTJ ILJ n VnVn n nV nnn7 Ci D ci IciData MZ3500 MFD interface block diagram FDC UPD765 22 «- o WindowUPD765 signal description Trigger motor on of the timer 555 Selects FDD MZ350CPort used in the MFD interface is as follows MFM recording methodControls during read, write, seek, and re- calibrate Media detection3500 Precompensate Circuit Control during seek and recalibrationVFO circuit Purpose String of data Pulses from the FDD Data windowVFO circuit configuration Filter Phase Detector Amplifier WindowMFM Mode BQAFM mode timing chart \\\\ 3DSC Side =Aload 76 iy 7 EH 77 / FFH \128Track 10 sector Indicates the byte position From the top of directoryIi Patat B144 6145 B146 B147 39 B148 B149 B150 B15139 B74 B75 1015General specification Data transmission formatMZS500 Example 7-bits, even parity, 1 stop bitOFF AC controlsStart 8251 AC MZ3500 Data output controlKTS 3SOO RXEN,UTR , T X E N200 9 6.3256 128Wl -» «--N8253 8253 OUTPrinter interfacing circuit AA3DAT DS7Data transfer timing General description of the parallel interfaceOutput I/O port map Clock circuit Schematic Read HoldWrite Hold SET DINMZ3500 PD1990AC Block diagram LSB MSBMmmil » GETE1 J3500 S I CGP I/O SFD 1/FSW2 SW1 On on CE332P OFF on MZ1P02 On OFF IO2824 OFF OFF DipswaSEC FD2\f Canbe in either state Description of each block Block diagramFunctions Switching regulator +5VAlarm generation circuit Timing chartKey Specification of keyboard controlAt rrn Key search timing 2s 2s22 21Key StrobeProtocol Key to sub CPU 132.522.5/-s Keyboard controller basic flow Keyboard controller signal description XTAL1 XTAL2 Reset INTPIN ALE DBO DB7 GNDOn OFF Procedure Sub-CPU sideShared RAM CRT inter face testAbnormal S C I I 00-FFReady O.H Abnormal test ending1 5 c * O DR O.7 ROM-IPL Main CPU Checker Flow Chart 1/2 Main CPU Checker Flow Chart M? 100101 M7*500Keyboard controller ROM test Keyboard testIPL Flow Chart Jump \ Boot Address System SEEK, Read ErrorError Load Iocs SEEK& ReadSUB CPU IPL Flow Chart 105LJ LJ LJ LJ LJ LJ LJ R R R R F1LU LU U LJ LlJ LJ U U U J l J J L i J L L j l J J L l J L L lRoB IwCAIO MZ-35OO Parts Guide LI S C R I P T I O N No Parts CodeLED PWB IE--or Ooss-zw MZ-3500 Parts CodeN T K QcnwConnector S C R I P T I O NMZ-3500 NO. Parts CodeParts Code A a N a DVH S N 7 4 0 6 N NEWCoos Part S C R I P T I O NMark Rank J9, MZ1K02,1K03,1K04,1K05 Key unit M2-3500SOC LSI RAMLA a NO. Parts CodeD e Tin Parts Code N a aMZ-3500 Sharp Corporation