Sharp MZ-3500 service manual CSP 2 Block Diagram, 3r00, DSP2 OUT, Cas Out

Page 37

M/3r>00

 

P r i o r i ty

 

 

 

Signal Name

 

 

36

M32

IN

Clock input 32MHz, 200 raster

37

FS

OUT

Graphic DRAM address multiplexer signal (High order 8 bits I ADS ADI 5] /low 3'der S hi"

 

 

 

ADO AD7] select signal )

38

DSP2

OUT

Display timing signal (In the CSP 2, the signal BLINK from GDC2 is delayed by 2 collor intervals to

 

 

 

create this signal )

39

CAS 2

OUT

Graphic D RAM CAS (COLUMN ADDRESS SELECT) signal

 

 

 

(Line address selection)

40

Vcc

IN

+ 5V supply

CSP 2 Block Diagram

S-RAM & CG control signal generator

 

 

 

 

 

 

 

 

Ci

' '

 

 

 

 

 

 

 

 

 

 

:

co

L

 

 

 

Jl

 

 

 

 

i 3

i6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

GDC1 &

 

 

 

 

 

Hexadecimal

 

™£

 

 

 

 

 

 

 

 

character

 

 

 

 

 

r* counter

 

 

 

 

display clock

 

 

 

 

 

 

 

O

 

generator

 

 

 

 

 

-a.

 

 

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32MHz

 

 

 

L>

 

 

 

 

 

 

200

Raster

 

 

 

 

 

 

 

 

 

 

Clock select

 

 

bill

circuit

GOC2&

 

 

 

 

 

 

 

 

 

3«32MHz

^

ClfCU1,

 

 

 

 

graphic display

 

*M n~,

*

^00/41 to

 

 

8/16

select

clock

 

 

4U(J

HasTer

 

rasters

 

 

generator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• 0

 

t

 

 

 

 

 

 

 

 

 

T

 

 

 

 

 

 

 

 

 

 

 

ft.

 

 

 

 

DBI2D

 

 

VWRO —C

 

 

 

CK

5

 

Cfi

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Oh

16

Q

 

 

 

 

 

 

 

 

 

1 O

I)

 

 

 

 

 

 

 

 

 

 

F

F

 

 

 

 

 

 

 

 

 

40/80

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K A S 2 —C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

F

'

Ubl 2 —C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DRAM

 

 

 

 

 

 

 

 

 

 

 

control signal

 

 

 

 

 

 

 

 

 

 

generator

 

 

 

 

 

 

 

 

 

 

 

' '

' •

 

 

 

 

 

,

c K Q

 

 

 

 

 

GDC2

 

 

 

 

 

 

 

 

 

Read

 

 

 

 

 

n

 

 

 

 

 

ignal

 

 

 

 

 

 

 

2 — 3

 

 

 

 

 

 

 

 

 

 

 

generator

 

 

 

F

 

 

 

 

 

 

 

 

 

)ECODER

 

 

 

 

 

 

 

 

 

 

 

 

 

n

h

P°

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L}\

 

CK

t f

^— Bl SC,

D- SOf

O- SHE

^

O—HB 1 A

- 42 -

Page 36 Page 38
Image 37
Page 36 Page 38
Contents Personal Computer Model Z-350 BACKUP, INIT, COPY, DEBUG, Killall TimerMemory VideoSlot Slot2 Refer to the page TIN Circuit DiagramLSI, 1C Cmosic SFDI/FSymbol PresetSdisp Change DispBase Basic Area RAMSystem UserMZ-1D07 MZ3500 System configuration of Model MS1 = D MSO = 0 L Software Memory ConfigurationTiming of Reset Signal ROM-IPL SD1 System Loading & CP/MFfff Bank SelectMAO Operational description SD3 RAM based BasicBank ROMMain Memory Mapper Block diagram Relation between MMR main memoryThis paragraph discusses main CPU I/O Main CPU and I/O portTable below describes address map Main CPU \m 0001MZ3500 Sub CPU and I/O portTo Reset Memory mapper MMRSP6102R-001 Block diagramAddress BUS CoabRAS ROW Address Select Line Address Select Signal MZ3500 Memory mapper MMR SP6102R-001 signal descriptionSrdy Pin No RO1B IN/OUTRO2B 1 1 1 1 0 KI1 Dl Do 17 D6 D5 A7 A6 A5A4A3A2AlAO H E X Uhus 1 OD2 Dl 1 1 1 1 1 0 FE do D4 D3 1 1 1 1 1 1 FF 14 I N D3MZ3500 Memory ROMIPL, RAMCOM, S-RAM select circuit CRT SpecificationAsci Summary of video display specificationBlue Dot pitchDot color designated by Graphic dotKA7 CH ATCH AI +,! AT A r + + G Ascii CG #1 FFFVideo RAM Structure of Vram #07FFA Structure of character Vram When read/write from GDC#0000 8bit Read/write by Z-80 via the GDC 640 x 200 dots display modeFV = 60 Hz 16KSetup of GCD master/slave 640 x 400 bits display mode FH = 20.92 kHz FV = 47.3 HzMaster/slave setup by combination O signal switchingGraphic V-RAM Address Crtc block diagramPage Master slice LSI CSP-1 SP6102C 002 signal description » CK CSP-1 Block DiagramCSH HSY2 2BLK2 LSI CSP-2 SP6012C-003 Signal Description3r00 CSP 2 Block DiagramDSP2 OUT CAS OUTGDC Graphic display controller UPD7220 signal description NK-CLC AD15ILC2AT~BTI CSR-1MAGEStructure CG Address Select CircuitCircuit description VsyncBlsc Character Vram select circuitRead/write from the Z-80 to V-RAM Set GDC command codeCsrw C 49H -COMMAND Code Return when all parameters were sentWrite C 23H Command Code Vecte C 6CH Command Code Fifo Empty?Explanation 60HVECTE. Dot address is structured on the screen Following manner Dot display program example-1P4 88H P5 HH I T E C 23HKind of line solid line Outline Floppy diskTJ ILJ n Ci D ci Ici VnVn n nV nnn7Data MZ3500 MFD interface block diagram 22 «- o Window FDC UPD765UPD765 signal description MZ350C Trigger motor on of the timer 555 Selects FDDPort used in the MFD interface is as follows MFM recording methodMedia detection Controls during read, write, seek, and re- calibrate3500 Precompensate Circuit Control during seek and recalibrationPurpose String of data Pulses from the FDD Data window VFO circuitFilter Phase Detector Amplifier Window VFO circuit configurationBQA MFM ModeFM mode timing chart \\\\ Aload Side =3DSC \128 76 iy 7 EH 77 / FFHTrack 10 sector Indicates the byte position From the top of directoryB144 6145 B146 B147 39 B148 B149 B150 B151 Ii Patat39 B74 B75 1015Data transmission format General specificationMZS500 Example 7-bits, even parity, 1 stop bitStart AC controlsOFF KTS MZ3500 Data output control8251 AC RXEN,UTR , T X E N 3SOO9 6.3 200256 128«--N Wl -»8253 OUT 8253AA3 Printer interfacing circuitDAT DS7Output General description of the parallel interfaceData transfer timing I/O port map Read Hold Clock circuit SchematicWrite Hold SET DINLSB MSB MZ3500 PD1990AC Block diagram» GETE1 J MmmilS I C 3500GP I/O SFD 1/FDipswa SW2 SW1 On on CE332P OFF on MZ1P02 On OFF IO2824 OFF OFFSEC FD2\f Canbe in either state Functions Block diagramDescription of each block +5V Switching regulatorTiming chart Alarm generation circuitAt rrn Specification of keyboard controlKey 2s 2s22 21 Key search timingKey Strobe22.5/-s 132.5Protocol Key to sub CPU Keyboard controller basic flow XTAL1 XTAL2 Reset INT Keyboard controller signal descriptionPIN ALE DBO DB7 GNDOn OFF Sub-CPU side ProcedureCRT inter face test Shared RAMAbnormal S C I I 00-FF1 5 c * O DR O.7 Abnormal test endingReady O.H ROM-IPL Main CPU Checker Flow Chart 1/2 100 Main CPU Checker Flow Chart M?M7*500 101Keyboard test Keyboard controller ROM testIPL Flow Chart SEEK, Read Error Jump \ Boot Address SystemError Load Iocs SEEK& Read105 SUB CPU IPL Flow ChartR R R R F1 LJ LJ LJ LJ LJ LJ LJU J l J J L i J L L j l J J L l J L L l LU LU U LJ LlJ LJ U UAIO IwCRoB MZ-35OO Parts Guide LI LED PWB No Parts CodeS C R I P T I O N IE--or Ooss-zw Parts Code MZ-3500N T K QcnwS C R I P T I O N ConnectorNO. Parts Code MZ-3500Parts Code A a N a DNEW VH S N 7 4 0 6 NMark Rank Part S C R I P T I O NCoos M2-3500 J9, MZ1K02,1K03,1K04,1K05 Key unitLSI RAM SOCLA a NO. Parts CodeD e Tin N a a Parts CodeMZ-3500 Sharp Corporation
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