Omega OME-PIO-D144 manual I/O Address Map, RESET\ Control Register, Address Read Write, Reset

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3.3The I/O Address Map

The I/O address of PIO/PISO series card is automatically assigned by the main board ROM BIOS. The I/O address can also be re-assigned by user.

It is strongly recommended to the user to not change the I/O address. The Plug & Play BIOS will assign proper I/O address to each OME- PIO/PISO series card very well. The I/O addresses of OME-PIO-D144 are

given as follows:

Address

Read

Write

WBase+0

RESET\ control register

Same

WBase+2

Aux control register

Same

WBase+3

Aux data register

Same

 

 

 

WBase+5

INT mask control register

Same

WBase+7

Aux pin status register

Same

WBase+0x2a

INT polarity control register

Same

 

 

 

WBase+0xc0

Read 8-bit data from D/I port

Write 8-bit data to D/O port

WBase+0xc4

Reserved

Select the active I/O port

WBase+0xc8

Reserved

I/O Port 0-5 direction control

WBase+0xcc

Reserved

I/O Port 6-11 direction control

WBase+0xd0

Reserved

I/O Port 12-17 direction control

Note. Refer to Sec. 3.1 for more information about wBase.

3.3.1RESET\ Control Register

(Read/Write): wBase+0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

RESET\

Note. Refer to Sec. 3.1 for more information about wBase.

When the PC is first powered up, the RESET\ signal is in Low-state. This will disable all D/I/O operations. The user has to set the RESET\ signal to High-state before any D/I/O command.

outp(wBase,1);

/*

RESET\=High Æ all D/I/O are enable now */

outp(wBase,0);

/*

RESET\=Low Æ all D/I/O are disable now */

OME-PIO-D144 User’s Manual (Ver.2.1, Sep/2001)

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Contents User’sGuide Benelux CanadaMexico Czech RepublicOME-PIO-D144 Table of Contents Demo Program Specifications All signals are TTL compatibleProduct Check List Hardware configuration Board LayoutEnable I/O Operation I/O Port LocationRefer to DEMO1.C for demo program O Architecture If INT signal is Low now Æ select the non-inverted input Interrupt OperationMake sure the initial level is High or Low Refer to DEMO3.C for source code Refer to DEMO4.C for source code CN1PC0 CN1PC1 CN1PC2 CN1PC3 If PC1 is active OME-DN-37 & OME-DN-50 Daughter BoardsOME-DB-37 OME-DB-8125OME-ADP-37/PCI & OME-ADP-50/PCI OME-DB-24P/24PD Isolated Input Board OME-PIO-D144OME-DB-24P OME-DB-24PD OME-DB-24R/24RD Relay Board OME-DB-24PR/24POR/24C OME-DB-24PRCOM OME-DB-24PR Daughter Board Comparison Table Pin Assignment VCCGND OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 PIO/PISO identification information How to Find the I/O AddressResource-allocated information PC’s physical slot informationOME-PISO-P32A32 OME-PIO-821OME-PISO-P32C32 OME-PISO-P8R8PIODriverInit PIODriverInit&wBoards, wSubVendor,wSubDevice,wSubAuxPIOGetConfigAddressSpace ShowPIOPISO Assignment of I/O Address Slot5 0x0A Slot6 0x08 Slot7 0x09 Slot8 0x07OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 I/O Address Map RESET\ Control RegisterRESET\ Address Read WriteINT Mask Control Register AUX Control RegisterAUX data Register CN1PC3 CN1PC2 CN1PC1 CN1PC0Aux Status Register Interrupt Polarity Control RegisterRead/Write 8-bit data Register Active I/O Port Control RegisterCN4PC CN4PB CN4PA CN3PC CN3PB CN3PA 9 I/O Selection Control RegisterCN2PC CN2PB CN2PA CN1PC CN1PB CN1PA CN6PC CN6PB CN6PA CN5PC CN5PB CN5PA\TC\LARGE\DEMO?\ \TC\LARGE\\TC\LARGE\LIB\ \TC\LARGE\LIB\PIO.HOME-PIO-D144.H Demo1 Use D/O of CN1 CN3 CN4 Demo2 Use D/O of CN1~CN6 PA/PB/PC Demo3 Interrupt demo1 COUNT=0Refer to Sec .5.1 for more information Demo4 Interrupt demo2 Refer to Sec .5.2 for more information Demo5 Interrupt demo3 CN1PC1 OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 Demo 6 Outport of CN1-CN6 OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 Demo10 Find Card Number OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 WARRANTY/DISCLAIMER Temperature