Omega OME-PIO-D144 manual CN1PC1

Page 46

for (;;)

{

printf("\n(CNT_L, CNT_H) = (%d,%d) (%d,%d) (%d,%d) (%d,%d) %x", CNT_L1,CNT_H1,CNT_L2,CNT_H2,CNT_L3,CNT_H3,CNT_L4,CNT_H4,

int_num);

if (kbhit()!=0) {getch(); break;}

}

outp(wBase+5,0);

/* disable all interrupt */

 

PIO_DriverClose();

 

 

}

 

 

/* ------------------------------------------------------------

*/

/* Use PC0 as external interrupt signal

*/

WORD init_low()

 

 

{

 

 

DWORD dwVal;

 

 

disable();

 

 

outp(wBase+5,0);

/* disable all interrupt */

 

if (wIrq<8)

 

 

{

irqmask=inp(A1_8259+1);

outp(A1_8259+1,irqmask & (0xff ^ (1 << wIrq))); setvect(wIrq+8, irq_service);

}

else

{

irqmask=inp(A1_8259+1);

/* IRQ2 */

outp(A1_8259+1,irqmask & 0xfb);

outp(A1_8259+1,irqmask & (0xff ^ (1 << wIrq))); irqmask=inp(A2_8259+1); outp(A2_8259+1,irqmask & (0xff ^ (1 << (wIrq-8)))); setvect(wIrq-8+0x70, irq_service);

}

invert=0x05;

 

/*

CN1_PC0 = non-inverte input */

outp(wBase+0x2a,invert);

/*

CN1_PC1

=

inverte input */

/*

CN1_PC2

= non-inverte input */

/*

CN1_PC3

= non-inverte input */

now_int_state=0x0a;

 

/* Now

CN1_PC0 = low

*/

/*

CN1_PC1

= high

 

*/

/*

CN1_PC2

= low

 

*/

/*

CN1_PC3

= high

 

*/

CNT_L1=CNT_L2=CNT_L3=CNT_L4=0;

/* low pulse count */

CNT_H1=CNT_H2=CNT_H3=CNT_H4=0;

/* high pulse count */

int_num=0;

/* enable interrupt PC0,PC1,PC2,PC3 of CN1 */

outp(wBase+5,0x0f);

enable();

 

 

}

 

 

void interrupt irq_service()

{

char cc;

int_num++;

new_int_state=inp(wBase+0x07)&0xff; int_c=new_int_state ^ now_int_state;

OME-PIO-D144 User’s Manual (Ver.2.1, Sep/2001)

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Contents User’sGuide Benelux CanadaMexico Czech RepublicOME-PIO-D144 Table of Contents Demo Program All signals are TTL compatible SpecificationsProduct Check List Hardware configuration Board LayoutI/O Port Location Enable I/O OperationRefer to DEMO1.C for demo program O Architecture Interrupt Operation If INT signal is Low now Æ select the non-inverted inputMake sure the initial level is High or Low Refer to DEMO3.C for source code Refer to DEMO4.C for source code CN1PC0 CN1PC1 CN1PC2 CN1PC3 If PC1 is active OME-DN-37 & OME-DN-50 Daughter BoardsOME-DB-37 OME-DB-8125OME-ADP-37/PCI & OME-ADP-50/PCI OME-PIO-D144 OME-DB-24P/24PD Isolated Input BoardOME-DB-24P OME-DB-24PD OME-DB-24R/24RD Relay Board OME-DB-24PR OME-DB-24PR/24POR/24CCOM OME-DB-24PR Daughter Board Comparison Table VCC Pin AssignmentGND OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 PIO/PISO identification information How to Find the I/O AddressResource-allocated information PC’s physical slot informationOME-PISO-P32A32 OME-PIO-821OME-PISO-P32C32 OME-PISO-P8R8PIODriverInit PIODriverInit&wBoards, wSubVendor,wSubDevice,wSubAuxPIOGetConfigAddressSpace ShowPIOPISO Assignment of I/O Address Slot5 0x0A Slot6 0x08 Slot7 0x09 Slot8 0x07OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 I/O Address Map RESET\ Control RegisterRESET\ Address Read WriteINT Mask Control Register AUX Control RegisterAUX data Register CN1PC3 CN1PC2 CN1PC1 CN1PC0Aux Status Register Interrupt Polarity Control RegisterRead/Write 8-bit data Register Active I/O Port Control RegisterCN4PC CN4PB CN4PA CN3PC CN3PB CN3PA 9 I/O Selection Control RegisterCN2PC CN2PB CN2PA CN1PC CN1PB CN1PA CN6PC CN6PB CN6PA CN5PC CN5PB CN5PA\TC\LARGE\DEMO?\ \TC\LARGE\\TC\LARGE\LIB\ \TC\LARGE\LIB\PIO.HOME-PIO-D144.H Demo1 Use D/O of CN1 CN3 CN4 Demo2 Use D/O of CN1~CN6 PA/PB/PC Demo3 Interrupt demo1 COUNT=0Refer to Sec .5.1 for more information Demo4 Interrupt demo2 Refer to Sec .5.2 for more information Demo5 Interrupt demo3 CN1PC1 OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 Demo 6 Outport of CN1-CN6 OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 Demo10 Find Card Number OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 WARRANTY/DISCLAIMER Temperature