Omega manual OME-PIO-D144.H

Page 36

4.1OME-PIO-D144.H

/* The header file for OME-PIO-D144 card */

#define Disable	0
#define Enable	1
#define D144	wBase+0x00
#define IO_SCR0	wBase+0xc8
#define IO_SCR1	wBase+0xcc
#define IO_SCR2	wBase+0xd0
#define AUX_CR	wBase+0x02
#define AUX_DR	wBase+0x03
#define INT_MCR	wBase+0x05
#define AUX_SR	wBase+0x07
#define INT_PCR	wBase+0x2a
#define RW_8BitDR	wBase+0xc0
#define ACT_IOPCR	wBase+0xc4
#define CN1_PA	0
#define CN1_PB	1
#define CN1_PC	2
#define CN2_PA	3
#define CN2_PB	4
#define CN2_PC	5
#define CN3_PA	6
#define CN3_PB	7
#define CN3_PC	8
#define CN4_PA	9
#define CN4_PB	10
#define CN4_PC	11
#define CN5_PA	12
#define CN5_PB	13
#define CN5_PC	14
#define CN6_PA	15
#define CN6_PB	16
#define CN6_PC	17

OME-PIO-D144 User’s Manual (Ver.2.1, Sep/2001)

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Contents User’sGuide Canada MexicoBenelux Czech RepublicOME-PIO-D144 Table of Contents Demo Program Specifications All signals are TTL compatibleProduct Check List Hardware configuration Board LayoutEnable I/O Operation I/O Port LocationRefer to DEMO1.C for demo program O Architecture If INT signal is Low now Æ select the non-inverted input Interrupt OperationMake sure the initial level is High or Low Refer to DEMO3.C for source code Refer to DEMO4.C for source code CN1PC0 CN1PC1 CN1PC2 CN1PC3 If PC1 is active Daughter Boards OME-DB-37OME-DN-37 & OME-DN-50 OME-DB-8125OME-ADP-37/PCI & OME-ADP-50/PCI OME-DB-24P/24PD Isolated Input Board OME-PIO-D144OME-DB-24P OME-DB-24PD OME-DB-24R/24RD Relay Board OME-DB-24PR/24POR/24C OME-DB-24PRCOM OME-DB-24PR Daughter Board Comparison Table Pin Assignment VCCGND OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 How to Find the I/O Address Resource-allocated informationPIO/PISO identification information PC’s physical slot informationOME-PIO-821 OME-PISO-P32C32OME-PISO-P32A32 OME-PISO-P8R8PIODriverInit PIODriverInit&wBoards, wSubVendor,wSubDevice,wSubAuxPIOGetConfigAddressSpace ShowPIOPISO Assignment of I/O Address Slot5 0x0A Slot6 0x08 Slot7 0x09 Slot8 0x07OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 RESET\ Control Register RESET\I/O Address Map Address Read WriteAUX Control Register AUX data RegisterINT Mask Control Register CN1PC3 CN1PC2 CN1PC1 CN1PC0Aux Status Register Interrupt Polarity Control RegisterRead/Write 8-bit data Register Active I/O Port Control Register9 I/O Selection Control Register CN2PC CN2PB CN2PA CN1PC CN1PB CN1PACN4PC CN4PB CN4PA CN3PC CN3PB CN3PA CN6PC CN6PB CN6PA CN5PC CN5PB CN5PA\TC\LARGE\ \TC\LARGE\LIB\\TC\LARGE\DEMO?\ \TC\LARGE\LIB\PIO.HOME-PIO-D144.H Demo1 Use D/O of CN1 CN3 CN4 Demo2 Use D/O of CN1~CN6 PA/PB/PC Demo3 Interrupt demo1 COUNT=0Refer to Sec .5.1 for more information Demo4 Interrupt demo2 Refer to Sec .5.2 for more information Demo5 Interrupt demo3 CN1PC1 OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 Demo 6 Outport of CN1-CN6 OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 Demo10 Find Card Number OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 WARRANTY/DISCLAIMER Temperature