Omega OME-PIO-D144 I/O Port Location, Enable I/O Operation, Refer to DEMO1.C for demo program

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2.2I/O Port Location

There are eighteen 8-bit I/O ports in the OME-PIO-D144. Every I/O port can be programmed as D/I or D/O port. When the PC is first powered up, all eighteen ports are used as D/I ports. The I/O port location is given as following:

Connector of OME-PIO-D144

PA0 to PA7

PB0 to PB7

PC0 to PC7

CN1

CN1_PA

CN1_PB

CN1_PC

CN2

CN2_PA

CN2_PB

CN2_PC

CN3

CN3_PA

CN3_PB

CN3_PC

CN4

CN4_PA

CN4_PB

CN4_PC

CN5

CN5_PA

CN5_PB

CN5_PC

CN6

CN6_PA

CN6_PB

CN6_PC

Refer to Sec. 2.1 for board layout & I/O port location.

Note: PC0, PC1, PC2, PC3 of CN1 can be used as interrupt signal source. Refer to Sec. 2.5 for more information.

2.3Enable I/O Operation

When the PC is first powered up, all operation of D/I/O port are disable. The enable/disable of D/I/O is controlled by the RESET\ signal. Refer to Sec. 3.3.1 for more information about RESET\ signal. The power-on states are given as following:

All D/I/O operations are disable

All eighteen D/I/O ports are configured as D/I port

All D/O latch register are undefined.(refer to Sec. 2.4)

The user has to perform some initialization before using these D/I/Os. The recommended steps are given as following:

Step 1: Make sure which ports are D/O ports.

Step 2: Enable all D/I/O operation.(refer to Sec. 3.3.1).

Step 3: Select the active port (refer to Sec. 3.3.8).

Step 4: Send initial-value to the D/O latch register of this active port. (Refer to Sec. 2.4 & Sec. 3.3.7)

Step 5: Repeat Step3 & Step4 for all D/O ports

Step 6: Configure all eighteen D/I/O ports to their expected D/I or D/O state. (Refer to Sec. 3.3.9)

Refer to DEMO1.C for demo program.

OME-PIO-D144 User’s Manual (Ver.2.1, Sep/2001)

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Contents User’sGuide Canada MexicoBenelux Czech RepublicOME-PIO-D144 Table of Contents Demo Program Product Check List SpecificationsAll signals are TTL compatible Hardware configuration Board LayoutRefer to DEMO1.C for demo program Enable I/O OperationI/O Port Location O Architecture Make sure the initial level is High or Low If INT signal is Low now Æ select the non-inverted inputInterrupt Operation Refer to DEMO3.C for source code Refer to DEMO4.C for source code CN1PC0 CN1PC1 CN1PC2 CN1PC3 If PC1 is active Daughter Boards OME-DB-37OME-DN-37 & OME-DN-50 OME-DB-8125OME-ADP-37/PCI & OME-ADP-50/PCI OME-DB-24P OME-DB-24PD OME-DB-24P/24PD Isolated Input BoardOME-PIO-D144 OME-DB-24R/24RD Relay Board COM OME-DB-24PR OME-DB-24PR/24POR/24COME-DB-24PR Daughter Board Comparison Table GND Pin AssignmentVCC OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 How to Find the I/O Address Resource-allocated informationPIO/PISO identification information PC’s physical slot informationOME-PIO-821 OME-PISO-P32C32OME-PISO-P32A32 OME-PISO-P8R8PIODriverInit PIODriverInit&wBoards, wSubVendor,wSubDevice,wSubAuxPIOGetConfigAddressSpace ShowPIOPISO Assignment of I/O Address Slot5 0x0A Slot6 0x08 Slot7 0x09 Slot8 0x07OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 RESET\ Control Register RESET\I/O Address Map Address Read WriteAUX Control Register AUX data RegisterINT Mask Control Register CN1PC3 CN1PC2 CN1PC1 CN1PC0Aux Status Register Interrupt Polarity Control RegisterRead/Write 8-bit data Register Active I/O Port Control Register9 I/O Selection Control Register CN2PC CN2PB CN2PA CN1PC CN1PB CN1PACN4PC CN4PB CN4PA CN3PC CN3PB CN3PA CN6PC CN6PB CN6PA CN5PC CN5PB CN5PA\TC\LARGE\ \TC\LARGE\LIB\\TC\LARGE\DEMO?\ \TC\LARGE\LIB\PIO.HOME-PIO-D144.H Demo1 Use D/O of CN1 CN3 CN4 Demo2 Use D/O of CN1~CN6 PA/PB/PC Demo3 Interrupt demo1 COUNT=0Refer to Sec .5.1 for more information Demo4 Interrupt demo2 Refer to Sec .5.2 for more information Demo5 Interrupt demo3 CN1PC1 OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 Demo 6 Outport of CN1-CN6 OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 Demo10 Find Card Number OME-PIO-D144 User’s Manual Ver.2.1, Sep/2001 WARRANTY/DISCLAIMER Temperature