Multi-Tech Systems MT5600BA-V92 manual +MR, +ER,+DR, and W commands

					Chapter 6 – S-Registers
S-Reg	Unit	Range	Default	Description
S95	decimal	0–255	0	Extended Result Codes Control: A bit set to a 1 in this register, in conjunction
				with the W command, enables the corresponding result code. The +MR, +ER, and
				+DR settings also control S95 bits 2, 3, and 5respectively. The more recent settings
				of +MR, +ER, and +DR, or host writing of S95 bits 2, 3, and 5, along with the W
				command setting, determine the corresponding actual result code reporting (see
				+MR, +ER,+DR, and W commands).
				Default:	0
				Bit 0	CONNECT result code indicates DCE speed instead of DTE speed.
				Bit 1	Append /ARQ to CONNECT XXX result code in error-correction mode
					(XXXX=rate).
				Bit 2	Enable +MCR: XXXX result code (XXXX=modulation) and +MRR: XXXX
					result code (XXXX=rate). (Also see +MR).
				Bit 3	Enable +ER XXXX result code (XXXX=protocol identifier).
				Bit 5	Enable +DR XXXX result code (XXXX=compression type).

Multi-Tech Systems, Inc. AT Commands Reference Guide (S000273G) 45