Cypress CY7C601xx, CY7C602xx, 1. Pin Assignments, Name, Description, Ssop, Pdip, Qsop

Cypress manual CY7C601xx, CY7C602xx, Features, Logic Block Diagram, Cypress Semiconductor Corporation Cypress manual Applications, Introduction, Conventions, CY7C601xx, CY7C602xx Cypress CY7C602xx manual Pinouts, CY7C60223, Pin PDIP, CY7C60113, Pin SSOP, 1. Package Configurations Top View, Pin SOIC Cypress manual CY7C601xx, CY7C602xx, 1. Pin Assignments, Name, Description, Ssop, Pdip, Qsop, Soic Cypress manual 1. Pin Assignments continued, CY7C601xx, CY7C602xx, Name, Description, Ssop, Pdip, Qsop, Soic Cypress manual 1. enCoRe II LV Register Summary, Addr, Default, CY7C601xx, CY7C602xx, Name, + Feedback Cypress manual 1. enCoRe II LV Register Summary continued, CY7C601xx, CY7C602xx, Addr, Name, Default, + Feedback Cypress CY7C601xx CPU Architecture, 1. CPU Registers and Register Name, 1. CPU Flags Register CPUF R/W, Bit 1 Zero Cypress CY7C602xx, CY7C601xx manual 2. CPU Accumulator Register CPUA, Index Register, 3. CPU X Register CPUX, Bit 70 X Cypress CY7C601xx, CY7C602xx Addressing Modes, 7. Source Immediate, Opcode, Operand, Examples, 9. Source Indexed Cypress manual 11. Destination Indexed, Example, Destination Direct Source Immediate, CY7C601xx, CY7C602xx, Opcode Cypress CY7C601xx Instruction Set Summary, 15. Source Indirect Post Increment, Destination Indirect Post Increment Cypress manual CY7C601xx, CY7C602xx, Cycles, Bytes, Flags, + Feedback Cypress CY7C601xx manual Flash Program Memory Organization, 1. Program Memory Space with Interrupt Vector Table, 0x1FFF Cypress CY7C602xx Flash, Srom, 2. Data Memory Organization, Stack begins here and grows upward, In-System Programming Cypress CY7C601xx manual SROM Function Descriptions, 2. SROM Function Parameters, Variable Name, SRAM Address, Return Codes Cypress CY7C602xx WriteBlock Function, 5. WriteBlock Parameters, EraseBlock Function, 6. EraseBlock Parameters, Mode, Name Cypress CY7C601xx manual 8. ProtectBlock Parameters, EraseAll Function, TableRead Function, 10. Table Read Parameters, Name Cypress manual SROM Table Read Description, CY7C601xx, CY7C602xx, Page 19 of Cypress manual CY7C601xx, CY7C602xx, eg ti Cypress CY7C602xx manual Clocking, Trim Values for the IOSCTR Register, Gain value for the register at location 0x38 3.3V = Cypress manual Clock Architecture Description, CPU Clock, CY7C601xx, CY7C602xx Cypress CY7C602xx 1. CPU Clock Block Diagram, 2. CPU Clock Configuration CPUCLKCR 0x30 R/W, Bit 71 Reserved, + Feedback Cypress CY7C601xx 3. OSC Control 0 OSCCR0 0x1E0 R/W continued, Bit 76 Reserved Bit 5 No Buzz, Sleep Timer, Sleep Period Cypress CY7C602xx, CY7C601xx 4. Clock IO Configuration CLKIOCR 0x32 R/W, Bit 75 Reserved, Interval Timer Clock ITMRCLK Cypress manual 2. Programmable Interval Timer Block Diagram, Timer Capture Clock TCAPCLK, CY7C601xx, CY7C602xx Cypress manual 5. Timer Clock Configuration TMRCLKCR 0x31 R/W, CY7C601xx, CY7C602xx, Page 27 of
Page 4
CY7C601xx, CY7C602xx

 

 

 

 

 

 

 

 

 

 

CY7C601xx, CY7C602xx

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6.1 Pin Assignments

 

 

 

 

 

 

 

 

 

Table 6-1. Pin Assignments

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

48

40

28

 

24

 

24

24

Name

Description

 

 

SSOP

PDIP

SSOP

QSOP

 

 

SOIC

PDIP

 

 

 

 

 

 

 

7

3

 

 

 

 

 

 

 

P4.0

GPIO Port 4—configured as a group (nibble)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

2

 

 

 

 

 

 

 

P4.1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

42

38

 

 

 

 

 

 

 

P4.2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

43

39

 

 

 

 

 

 

 

P4.3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

34

30

 

 

19

 

18

1

P3.0

GPIO Port 3—configured as a group (byte)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

35

31

 

 

20

 

19

2

P3.1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

36

32

 

 

 

 

 

 

 

P3.2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

37

33

 

 

 

 

 

 

 

P3.3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

38

34

24

 

 

 

 

 

 

P3.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

39

35

25

 

 

 

 

 

 

P3.5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

40

36

26

 

 

 

 

 

 

P3.6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

41

37

27

 

 

 

 

 

 

P3.7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

11

 

 

11

 

11

18

P2.0

GPIO Port 2—configured as a group (byte)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

10

 

 

10

 

10

17

P2.1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

9

 

 

 

 

 

 

 

P2.2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

8

 

 

 

 

 

 

 

P2.3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

7

5

 

 

 

 

 

 

P2.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

6

4

 

 

 

 

 

 

P2.5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

5

3

 

 

 

 

 

 

P2.6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

4

2

 

 

 

 

 

 

P2.7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

25

21

15

 

14

 

13

20

P1.0

GPIO Port 1 bit 0

 

 

 

 

 

 

 

 

 

 

 

 

If this pin is used as a general purpose output it draws current.

 

 

 

 

 

 

 

 

 

 

 

It is, therefore, configured as an input to reduce current draw.

 

26

22

16

 

15

 

14

21

P1.1

GPIO Port 1 bit 1

 

 

 

 

 

 

 

 

 

 

 

 

If this pin is used as a general purpose output it draws current.

 

 

 

 

 

 

 

 

 

 

 

It is, therefore, configured as an input to reduce current draw.

 

28

24

18

 

17

 

16

23

P1.2

GPIO Port 1 bit 2

 

 

 

 

 

 

 

 

 

 

 

 

 

29

25

19

 

18

 

17

24

P1.3/SSEL

GPIO Port 1 bit 3—Configured individually

 

 

 

 

 

 

 

 

 

 

 

 

Alternate function is SSEL signal of the SPI bus.

 

30

26

20

 

21

 

20

3

P1.4/SCLK

GPIO Port 1 bit 4—Configured individually

 

 

 

 

 

 

 

 

 

 

 

 

Alternate function is SCLK signal of the SPI bus.

 

31

27

21

 

22

 

21

4

P1.5/SMOSI

GPIO Port 1 bit 5—Configured individually

 

 

 

 

 

 

 

 

 

 

 

 

Alternate function is SMOSI signal of the SPI bus.

 

32

28

22

 

23

 

22

5

P1.6/SMISO

GPIO Port 1 bit 6—Configured individually

 

 

 

 

 

 

 

 

 

 

 

 

Alternate function is SMISO signal of the SPI bus.

 

33

29

23

 

24

 

23

6

P1.7

GPIO Port 1 bit 7—Configured individually

 

 

 

 

 

 

 

 

 

 

 

 

TTL voltage threshold.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document 38-16016 Rev. *E

Page 4 of 68

[+] Feedback

Page 3 Page 5
Image 4
Page 3 Page 5
Contents 1. Features 2. Logic Block DiagramCY7C601xx, CY7C602xx Cypress Semiconductor Corporation4. Introduction 3. Applications5. Conventions Figure 6-1. Package Configurations Top View 6. PinoutsCY7C60223 24-Pin PDIPCY7C601xx, CY7C602xx 6.1 Pin AssignmentsTable 6-1. Pin Assignments NameTable 6-1. Pin Assignments continued Default 7. Register SummaryTable 7-1. enCoRe II LV Register Summary AddrTable 7-1. enCoRe II LV Register Summary continued 8. CPU Architecture 9. CPU Registers9.1 Flags Register Table 8-1. CPU Registers and Register Name9.1.1 Accumulator Register Table 9-2. CPU Accumulator Register CPUA9.1.2 Index Register Table 9-3. CPU X Register CPUX9.2 Addressing Modes 9.2.1 Source ImmediateTable 9-7. Source Immediate Opcode9.2.5 Destination Indexed Table 9-11. Destination IndexedExample 9.2.6 Destination Direct Source Immediate10. Instruction Set Summary 9.2.9 Source Indirect Post IncrementTable 9-15. Source Indirect Post Increment 9.2.10 Destination Indirect Post IncrementCY7C601xx, CY7C602xx 11. Memory Organization 11.1 Flash Program Memory OrganizationFigure 11-1. Program Memory Space with Interrupt Vector Table 0x1FFF11.2 Data Memory Organization 11.3 Flash11.4 SROM Figure 11-2. Data Memory Organization11.5.1 SWBootReset Function 11.5 SROM Function DescriptionsTable 11-2. SROM Function Parameters Variable NameSettings 11.5.3 WriteBlock FunctionTable 11-5. WriteBlock Parameters 11.5.4 EraseBlock FunctionTable 11-8. ProtectBlock Parameters 11.5.6 EraseAll Function11.5.7 TableRead Function Table 11-10. Table Read Parameters11.6 SROM Table Read Description Page 19 ofeg ti Table 12-1. Oscillator Trim Values vs. Voltage Settings 12. Clocking12.1 Trim Values for the IOSCTR Register Gain value for the register at location 0x38 3.3V =12.2 Clock Architecture Description 12.2.1 CPU ClockFigure 12-1. CPU Clock Block Diagram Table 12-2. CPU Clock Configuration CPUCLKCR 0x30 R/WBit 71 Reserved Table 12-3. OSC Control 0 OSCCR0 0x1E0 R/WSleep Timer Sleep Timer ClockCPU when Internal Table 12-3. OSC Control 0 OSCCR0 0x1E0 R/W continued12.2.2 Interval Timer Clock ITMRCLK Table 12-4. Clock IO Configuration CLKIOCR 0x32 R/WBit 75 Reserved 12.2.3 Timer Capture Clock TCAPCLK Figure 12-2. Programmable Interval Timer Block DiagramFigure 12-3. Timer Capture Block Diagram Table 12-5. Timer Clock Configuration TMRCLKCR 0x31 R/W Page 27 ofXGM Setting 12.2.4 Internal Clock TrimTable 12-6. IOSC Trim IOSCTR 0x34 R/W Bit 40 Gain12.2.6 LPOSC Trim 12.3 CPU Clock During Sleep ModeTable 12-8. LPOSC Trim LPOSCTR 0x36 R/W 13. Reset Table 13-1. System Status and Control Register CPUSCR 0xFF R/WBit 7 GIES Bit 5 WDRS13.1 Power On Reset 13.2 Watchdog Timer ResetTable 13-2. Reset Watchdog Timer RESWDT 0xE3 W 14. Sleep Mode14.1.1 Low Power in Sleep Mode 14.1 Sleep SequenceCPUCLK IOW SLEEP BRQ BRA PD Figure 14-1. Sleep Timing14.2 Wakeup Sequence Figure 14-2. Wakeup Timing15. Low Voltage Detect Control Table 15-1. Low Voltage Control Register LVDCR 0x1E3 R/WBit 76 Reserved Bit 54 PORLEV10 Bit 20 VM2015.1 POR Compare State 15.2 ECO Trim RegisterTable 15-2. Voltage Monitor Comparators Register VLTCMP 0x1E4 R Bit 72 Reserved Bit 1 LVD16. General Purpose IO Ports 16.1 Port Data Registers16.1.1 P0 Data Table 16-1. P0 Data Register P0DATA0x00 R/W16.2 GPIO Port Configuration 16.2.1 Int Enable16.1.3 P2 Data Table 16-3. P2 Data Register P2DATA 0x02 R/W16.2.7 Output Enable 16.2.6 Pull Up EnableFigure 16-1. GPIO Block Diagram 16.2.9 P0.0/CLKIN ConfigurationTable 16-7. P0.1/CLKOUT Configuration P01CR 0x06 R/W 16.2.10 P0.1/CLKOUT Configuration16.2.11 P0.2/INT0-P0.4/INT2 Configuration 16.2.12 P0.5/TIO0-P0.6/TIO1 Configuration 16.2.13 P0.7 ConfigurationTable 16-10. P0.7 Configuration P07CR 0x0C R/W 16.2.14 P1.0 Configuration16.2.15 P1.1 Configuration Table 16-12. P1.1 Configuration P11CR 0x0E R/W16.2.16 P1.2 Configuration Table 16-13. P1.2 Configuration P12CR 0x0F R/W16.2.18 P1.4-P1.6 Configuration SCLK, SMOSI, SMISO Table 16-15. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W16.2.19 P1.7 Configuration Table 16-16. P1.7 Configuration P17CR 0x14 R/W16.2.21 P3 Configuration Table 16-18. P3 Configuration P3CR 0x16 R/W16.2.22 P4 Configuration Table 16-19. P4 Configuration P4CR 0x17 R/WFigure 17-1. SPI Block Diagram 17. Serial Peripheral Interface SPI17.2 SPI Configure Register Table 17-2. SPI Configure Register SPICR 0x3D R/W17.1 SPI Data Register Table 17-1. SPI Data Register SPIDATA 0x3C R/WTable 17-3. SPI Mode Timing vs. LSB First, CPOL, and CPHA DiagramCPHA CPOL18. Timer Registers 17.3 SPI Interface PinsFigure 18-1. 16-Bit Free Running Counter Block Diagram Table 18-1. Free Running Timer Low Order Byte FRTMRL 0x20 R/WTable 18-2. Free Running Timer High Order Byte FRTMRH 0x21 R/W Figure 18-2. Time Capture Block DiagramTable 18-3. Timer Configuration TMRCR 0x2A R/W 18.1.2 Time CaptureTable 18-4. Capture Interrupt Enable TCAPINTE 0x2B R/W Table 18-5. Timer Capture 0 Rising TCAP0R 0x22 R/WTable 18-6. Timer Capture 1 Rising TCAP1R 0x23 R/W Table 18-7. Timer Capture 0 Falling TCAP0F 0x24 R/WTable 18-8. Timer Capture 1 Falling TCAP1F 0x25 R/W 18.1.3 Programmable Interval TimerTable 18-10. Programmable Interval Timer Low PITMRL 0x26 R Table 18-9. Capture Interrupt Status TCAPINTS 0x2C R/WTable 18-12. Programmable Interval Reload Low PIRL 0x28 R/W Table 18-11. Programmable Interval Timer High PITMRH 0x27 RTable 18-13. Programmable Interval Reload High PIRH 0x29 R/W Figure 18-3. Timer Functional Sequence Diagram Page 52 ofFigure 18-4. 16-Bit Free Running Counter Loading Timing Diagram Figure 18-5. Memory Mapped Registers Read and Write Timing DiagramFigure 19-1. Interrupt Controller Block Diagram 19. Interrupt Controller19.1 Architectural Description Table 19-1. Interrupt Priorities, Address, and Name19.2 Interrupt Processing 19.3 Interrupt Latency19.4 Interrupt Registers Table 19-2. Interrupt Clear 0 INTCLR0 0xDA R/WTable 19-3. Interrupt Clear 1 INTCLR1 0xDB R/W Interrupt Clear 2 INTCLR2 0xDC R/W19.4.2 Interrupt Mask Registers Table 19-5. Interrupt Mask 3 INTMSK3 0xDE R/WTable 19-7. Interrupt Mask 1 INTMSK1 0xE1 R/W Table 19-6. Interrupt Mask 2 INTMSK2 0xDF R/WPage 57 of 19.4.3 Interrupt Vector Clear Register Table 19-8. Interrupt Mask 0 INTMSK0 0xE0 R/WTable 19-9. Interrupt Vector Clear Register INTVC 0xE2 R/W 20.1 DC Characteristics 20. Absolute Maximum RatingsParameter Conditions20.2 AC Characteristics ClockSPI Timing Figure 20-1. Clock TimingFigure 20-2. GPIO Timing Diagram SCK CPOL=0SCK CPOL=1 MOSI MISOMOSI MISOSS SCK CPOL=0 SCK CPOL=1 MOSI MISO MSB21. Ordering Information 22. Package HandlingSCK CPOL=0 SCK CPOL=1 MOSI MSB23. Package Diagrams Figure 23-1. 24-Pin 300-Mil SOIC S13Figure 23-2. 24-Pin 300-Mil PDIP P13 3. DIMENSIONS IN INCHESFigure 23-4. 28-Pin 5.3 mm Shrunk Small Outline Package O28 Figure 23-3. 24-Pin QSOP O241Page 65 of Figure 23-6. 48-Pin Shrunk Small Outline Package O48 Figure 23-5. 40-Pin 600-Mil Molded DIP P17Page 66 of 24. Document History Page Document NumberOrig. of SubmissionSales, Solutions, and Legal Information PSoC SolutionsWorldwide Sales and Design Support Products
Top Page Image Contents