CY7C601xx, CY7C602xx
7. Register Summary
Table 7-1. enCoRe II LV Register Summary
The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF.
Addr | Name | 7 | 6 | 5 | 4 | 3 |
| 2 | 1 | 0 | R/W | Default |
|
00 | P0DATA | P0.7 | P0.6/TIO1 | P0.5/TIO0 | P0.4/INT2 | P0.3/INT1 |
| P0.2/INT0 | P0.1/ | P0.0/CLKIN | bbbbbbbb | 00000000 |
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| CLKOUT |
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01 | P1DATA | P1.7 | P1.6/SMISO | P1.5/SMOSI | P1.4/SCLK | P1.3/SSEL |
| P1.2 | P1.1 | P1.0 | bbbbbbbb | 00000000 |
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02 | P2DATA |
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| bbbbbbbb | 00000000 |
| ||||
03 | P3DATA |
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| bbbbbbbb | 00000000 |
| ||||
04 | P4DATA |
| Reserved |
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| 00000000 |
| ||||
05 | P00CR | Reserved | Int Enable | Int Act Low | TTL Thresh | High Sink |
| Open Drain | Pull up | Output | 00000000 |
| |
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| Enable | Enable |
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06 | P01CR | CLK Output | Int Enable | Int Act Low | TTL Thresh | High Sink |
| Open Drain | Pull Up | Output | bbbbbbbb | 00000000 |
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| Enable | Enable |
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P02CR– | Reserved | Int Act Low | TTL Thresh | Reserved |
| Open Drain | Pull Up | Output | 00000000 |
| |||
| P04CR |
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| Enable | Enable |
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P05CR– | TIO Output | Int Enable | Int Act Low | TTL Thresh | Reserved |
| Open Drain | Pull Up | Output | 00000000 |
| ||
| P06CR |
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| Enable | Enable |
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|
0C | P07CR | Reserved | Int Enable | Int Act Low | TTL Thresh | Reserved |
| Open Drain | Pull Up | Output | 00000000 |
| |
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| Enable | Enable |
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|
0D | P10CR | Reserved | Int Enable | Int Act Low |
| Reserved |
| Output | 00000000 |
| |||
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| Enable |
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0E | P11CR | Reserved | Int Enable | Int Act Low | Reserved |
| Open Drain | Reserved | Output | 00000000 |
| ||
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| Enable |
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0F | P12CR | CLK Output | Int Enable | Int Act Low | TTL | Reserved |
| Open Drain | Pull Up | Output | 00000000 |
| |
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| Threshold |
|
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| Enable | Enable |
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10 | P13CR | Reserved | Int Enable | Int Act Low | Reserved | High Sink |
| Open Drain | Pull Up | Output | 00000000 |
| |
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| Enable | Enable |
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P14CR– | SPI Use | Int Enable | Int Act Low | Reserved | High Sink |
| Open Drain | Pull Up | Output | 00000000 |
| ||
| P16CR |
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| Enable | Enable |
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14 | P17CR | Reserved | Int Enable | Int Act Low | Reserved | High Sink |
| Open Drain | Pull Up | Output | 00000000 |
| |
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| Enable | Enable |
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15 | P2CR | Reserved | Int Enable | Int Act Low | TTL Thresh | High Sink |
| Open Drain | Pull Up | Output | 00000000 |
| |
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| Enable | Enable |
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16 | P3CR | Reserved | Int Enable | Int Act Low | TTL Thresh | High Sink |
| Open Drain | Pull Up | Output | 00000000 |
| |
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| Enable | Enable |
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17 | P4CR | Reserved | Int Enable | Int Act Low | TTL Thresh | Reserved |
| Open Drain | Pull Up | Output | 00000000 |
| |
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| Enable | Enable |
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20 | FRTMRL |
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| Free Running Timer [7:0] |
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| bbbbbbbb | 00000000 |
| ||
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21 | FRTMRH |
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| Free Running Timer [15:8] |
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| bbbbbbbb | 00000000 |
| ||
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22 | TCAP0R |
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| Capture 0 Rising [7:0] |
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| rrrrrrrr | 00000000 |
| ||
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| ||
23 | TCAP1R |
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| Capture 1 Rising [7:0] |
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| rrrrrrrr | 00000000 |
| ||
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24 | TCAP0F |
|
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| Capture 0 Falling [7:0] |
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| rrrrrrrr | 00000000 |
| ||
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25 | TCAP1F |
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| Capture 1 Falling [7:0] |
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| rrrrrrrr | 00000000 |
| ||
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| ||
26 | PITMRL |
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| Prog Interval Timer [7:0] |
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| rrrrrrrr | 00000000 |
| ||
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| |
27 | PITMRH |
| Reserved |
|
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| Prog Interval Timer [11:8] |
| 00000000 |
| |||
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28 | PIRL |
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| Prog Interval [7:0] |
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| bbbbbbbb | 00000000 |
| ||
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| |
29 | PIRH |
| Reserved |
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| Prog Interval [11:8] |
| 00000000 |
| |||
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2A | TMRCR | First Edge | Cap0 |
|
| Reserved |
| 00000000 |
| ||||
|
| Hold |
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| Enable |
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2B | TCAPINTE |
| Reserved |
| Cap1 Fall |
| Cap1 Rise | Cap0 Fall | Cap0 Rise | 00000000 |
| ||
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|
| Active |
| Active | Active | Active |
|
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|
2C | TCAPINTS |
| Reserved |
| Cap1 Fall |
| Cap1 Rise | Cap0 Fall | Cap0 Rise | 00000000 |
| ||
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| Active |
| Active | Active | Active |
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30 | CPUCLKCR |
|
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| Reserved |
|
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| CPU | 00000000 |
| |
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| CLK Select |
|
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31 | TMRCLKCR | TCAPCLK Divider | TCAPCLK Select | ITMRCLK Divider | ITMRCLK Select | bbbbbbbb | 10001111 |
| |||||
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32 | CLKIOCR |
| Reserved |
| XOSC | XOSC |
| EFTB | CLKOUT Select | 00000000 |
| ||
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| Select | Enable |
| Disabled |
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Document |
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| Page 6 of 68 |
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