Cypress CY7C601xx manual 16.2.12 P0.5/TIO0-P0.6/TIO1 Configuration, 16.2.13 P0.7 Configuration

Page 40
16.2.12 P0.5/TIO0–P0.6/TIO1 Configuration

CY7C601xx, CY7C602xx

16.2.12 P0.5/TIO0–P0.6/TIO1 Configuration

Table 16-9. P0.5/TIO0–P0.6/TIO1 Configuration (P05CR–P06CR) [0x0A–0x0B] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

TIO Output

Int Enable

Int Act Low

TTL Thresh

Reserved

Open Drain

Pull up Enable

Output Enable

Read/Write

R/W

R/W

R/W

R/W

–

R/W

R/W

R/W

Default

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

These registers control the operation of pins P0.5 through P0.6, respectively.

P0.5 and P0.6 are shared with TIO0 and TIO1 respectively. To use these pins as capture timer inputs, configure them as inputs by clearing the corresponding Output Enable. To use TIO0 and TIO1 as timer outputs, set the TIOx Output and Output Enable bits. If these pins are configured as outputs and the TIO Output bit is clear, firmware controls the TIO0 and TIO1 inputs by writing the value to the P0.5 and P0.6 data bits in the P0 Data Register.

Regardless of whether either pin is used as a TIO or GPIO pin the Int Enable, Int Act Low, TTL Threshold, Open Drain, and Pull up Enable control the behavior of the pin.

TIO0(P0.5) when enabled outputs a positive pulse from the 1024 μs interval timer. This is the same signal that is used internally to generate the 1024 μs timer interrupt. This signal is not gated by the interrupt enable state. The pulse is active for one cycle of the capture timer clock.

TIO1(P0.6) when enabled outputs a positive pulse from the programmable interval timer. This is the same signal that is used internally to generate the programmable timer interval interrupt. This signal is not gated by the interrupt enable state.The pulse is active for one cycle of the interval timer clock.

The P0.5/TIO0 and P0.6/TIO1 pins are individually configured with the P05CR (0x0A) and P06CR (0x0B), respectively.

16.2.13 P0.7 Configuration

Table 16-10. P0.7 Configuration (P07CR) [0x0C] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

Reserved

Int Enable

Int Act Low

TTL Thresh

Reserved

Open Drain

Pull up Enable

Output Enable

Read/Write

–

R/W

R/W

R/W

–

R/W

R/W

R/W

Default

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

This register controls the operation of pin P0.7.

16.2.14 P1.0 Configuration

Table 16-11. P1.0 Configuration (P10CR) [0x0D] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

Reserved

Int Enable

Int Act Low

 

Reserved

 

P1.0 and P1.1

Output Enable

 

 

 

 

 

 

 

Pull Up Enable

 

Read/Write

R/W

R/W

R/W

–

–

–

–

R/W

Default

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

This register controls the operation of the P1.0 pin. Bit1: P1.0 and P1.1 Pull Up Enable

0 = Disable the P1.0 and P1.1 pull up resistors.

1 = Enable the internal pull up resistors for both the P1.0 and P1.1. Each of the P1.0 and P1.1 pins is pulled up with RUP1 (see DC Characteristics on page 59).

Note There is no 2 mA sourcing capability on this pin. The pin can only sink 5 mA at VOL3 (see DC Characteristics on page 59) The P1.0 is an open drain only output. It actively drives a signal low, but cannot actively drive a signal high.

If this pin is used as a general purpose output, it draws current. It is therefore configured as an input to reduce current draw.

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Contents 1. Features 2. Logic Block DiagramCY7C601xx, CY7C602xx Cypress Semiconductor Corporation4. Introduction 3. Applications5. Conventions Figure 6-1. Package Configurations Top View 6. PinoutsCY7C60223 24-Pin PDIPCY7C601xx, CY7C602xx 6.1 Pin AssignmentsTable 6-1. Pin Assignments NameTable 6-1. Pin Assignments continued Default 7. Register SummaryTable 7-1. enCoRe II LV Register Summary AddrTable 7-1. enCoRe II LV Register Summary continued 8. CPU Architecture 9. CPU Registers9.1 Flags Register Table 8-1. CPU Registers and Register Name9.1.1 Accumulator Register Table 9-2. CPU Accumulator Register CPUA9.1.2 Index Register Table 9-3. CPU X Register CPUX9.2 Addressing Modes 9.2.1 Source ImmediateTable 9-7. Source Immediate Opcode9.2.5 Destination Indexed Table 9-11. Destination IndexedExample 9.2.6 Destination Direct Source Immediate10. Instruction Set Summary 9.2.9 Source Indirect Post IncrementTable 9-15. Source Indirect Post Increment 9.2.10 Destination Indirect Post IncrementCY7C601xx, CY7C602xx 11. Memory Organization 11.1 Flash Program Memory OrganizationFigure 11-1. Program Memory Space with Interrupt Vector Table 0x1FFF11.2 Data Memory Organization 11.3 Flash11.4 SROM Figure 11-2. Data Memory Organization11.5.1 SWBootReset Function 11.5 SROM Function DescriptionsTable 11-2. SROM Function Parameters Variable NameSettings 11.5.3 WriteBlock FunctionTable 11-5. WriteBlock Parameters 11.5.4 EraseBlock FunctionTable 11-8. ProtectBlock Parameters 11.5.6 EraseAll Function11.5.7 TableRead Function Table 11-10. Table Read Parameters11.6 SROM Table Read Description Page 19 ofeg ti Table 12-1. Oscillator Trim Values vs. Voltage Settings 12. Clocking12.1 Trim Values for the IOSCTR Register Gain value for the register at location 0x38 3.3V =12.2 Clock Architecture Description 12.2.1 CPU ClockFigure 12-1. CPU Clock Block Diagram Table 12-2. CPU Clock Configuration CPUCLKCR 0x30 R/WBit 71 Reserved Table 12-3. OSC Control 0 OSCCR0 0x1E0 R/WSleep Timer Sleep Timer ClockCPU when Internal Table 12-3. OSC Control 0 OSCCR0 0x1E0 R/W continued12.2.2 Interval Timer Clock ITMRCLK Table 12-4. Clock IO Configuration CLKIOCR 0x32 R/WBit 75 Reserved 12.2.3 Timer Capture Clock TCAPCLK Figure 12-2. Programmable Interval Timer Block DiagramFigure 12-3. Timer Capture Block Diagram Table 12-5. Timer Clock Configuration TMRCLKCR 0x31 R/W Page 27 ofXGM Setting 12.2.4 Internal Clock TrimTable 12-6. IOSC Trim IOSCTR 0x34 R/W Bit 40 Gain12.2.6 LPOSC Trim 12.3 CPU Clock During Sleep ModeTable 12-8. LPOSC Trim LPOSCTR 0x36 R/W 13. Reset Table 13-1. System Status and Control Register CPUSCR 0xFF R/WBit 7 GIES Bit 5 WDRS13.1 Power On Reset 13.2 Watchdog Timer ResetTable 13-2. Reset Watchdog Timer RESWDT 0xE3 W 14. Sleep Mode14.1.1 Low Power in Sleep Mode 14.1 Sleep SequenceCPUCLK IOW SLEEP BRQ BRA PD Figure 14-1. Sleep Timing14.2 Wakeup Sequence Figure 14-2. Wakeup Timing15. Low Voltage Detect Control Table 15-1. Low Voltage Control Register LVDCR 0x1E3 R/WBit 76 Reserved Bit 54 PORLEV10 Bit 20 VM2015.1 POR Compare State 15.2 ECO Trim RegisterTable 15-2. Voltage Monitor Comparators Register VLTCMP 0x1E4 R Bit 72 Reserved Bit 1 LVD16. General Purpose IO Ports 16.1 Port Data Registers16.1.1 P0 Data Table 16-1. P0 Data Register P0DATA0x00 R/W16.2 GPIO Port Configuration 16.2.1 Int Enable16.1.3 P2 Data Table 16-3. P2 Data Register P2DATA 0x02 R/W16.2.7 Output Enable 16.2.6 Pull Up EnableFigure 16-1. GPIO Block Diagram 16.2.9 P0.0/CLKIN ConfigurationTable 16-7. P0.1/CLKOUT Configuration P01CR 0x06 R/W 16.2.10 P0.1/CLKOUT Configuration16.2.11 P0.2/INT0-P0.4/INT2 Configuration 16.2.12 P0.5/TIO0-P0.6/TIO1 Configuration 16.2.13 P0.7 ConfigurationTable 16-10. P0.7 Configuration P07CR 0x0C R/W 16.2.14 P1.0 Configuration16.2.15 P1.1 Configuration Table 16-12. P1.1 Configuration P11CR 0x0E R/W16.2.16 P1.2 Configuration Table 16-13. P1.2 Configuration P12CR 0x0F R/W16.2.18 P1.4-P1.6 Configuration SCLK, SMOSI, SMISO Table 16-15. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W16.2.19 P1.7 Configuration Table 16-16. P1.7 Configuration P17CR 0x14 R/W16.2.21 P3 Configuration Table 16-18. P3 Configuration P3CR 0x16 R/W16.2.22 P4 Configuration Table 16-19. P4 Configuration P4CR 0x17 R/WFigure 17-1. SPI Block Diagram 17. Serial Peripheral Interface SPI17.2 SPI Configure Register Table 17-2. SPI Configure Register SPICR 0x3D R/W17.1 SPI Data Register Table 17-1. SPI Data Register SPIDATA 0x3C R/WTable 17-3. SPI Mode Timing vs. LSB First, CPOL, and CPHA DiagramCPHA CPOL18. Timer Registers 17.3 SPI Interface PinsFigure 18-1. 16-Bit Free Running Counter Block Diagram Table 18-1. Free Running Timer Low Order Byte FRTMRL 0x20 R/WTable 18-2. Free Running Timer High Order Byte FRTMRH 0x21 R/W Figure 18-2. Time Capture Block DiagramTable 18-3. Timer Configuration TMRCR 0x2A R/W 18.1.2 Time CaptureTable 18-4. Capture Interrupt Enable TCAPINTE 0x2B R/W Table 18-5. Timer Capture 0 Rising TCAP0R 0x22 R/WTable 18-6. Timer Capture 1 Rising TCAP1R 0x23 R/W Table 18-7. Timer Capture 0 Falling TCAP0F 0x24 R/WTable 18-8. Timer Capture 1 Falling TCAP1F 0x25 R/W 18.1.3 Programmable Interval TimerTable 18-10. Programmable Interval Timer Low PITMRL 0x26 R Table 18-9. Capture Interrupt Status TCAPINTS 0x2C R/WTable 18-12. Programmable Interval Reload Low PIRL 0x28 R/W Table 18-11. Programmable Interval Timer High PITMRH 0x27 RTable 18-13. Programmable Interval Reload High PIRH 0x29 R/W Figure 18-3. Timer Functional Sequence Diagram Page 52 ofFigure 18-4. 16-Bit Free Running Counter Loading Timing Diagram Figure 18-5. Memory Mapped Registers Read and Write Timing DiagramFigure 19-1. Interrupt Controller Block Diagram 19. Interrupt Controller19.1 Architectural Description Table 19-1. Interrupt Priorities, Address, and Name19.2 Interrupt Processing 19.3 Interrupt Latency19.4 Interrupt Registers Table 19-2. Interrupt Clear 0 INTCLR0 0xDA R/WTable 19-3. Interrupt Clear 1 INTCLR1 0xDB R/W Interrupt Clear 2 INTCLR2 0xDC R/W19.4.2 Interrupt Mask Registers Table 19-5. Interrupt Mask 3 INTMSK3 0xDE R/WTable 19-7. Interrupt Mask 1 INTMSK1 0xE1 R/W Table 19-6. Interrupt Mask 2 INTMSK2 0xDF R/WPage 57 of 19.4.3 Interrupt Vector Clear Register Table 19-8. Interrupt Mask 0 INTMSK0 0xE0 R/WTable 19-9. Interrupt Vector Clear Register INTVC 0xE2 R/W 20.1 DC Characteristics 20. Absolute Maximum RatingsParameter Conditions20.2 AC Characteristics ClockSPI Timing Figure 20-1. Clock TimingFigure 20-2. GPIO Timing Diagram SCK CPOL=0SCK CPOL=1 MOSI MISOMOSI MISOSS SCK CPOL=0 SCK CPOL=1 MOSI MISO MSB21. Ordering Information 22. Package HandlingSCK CPOL=0 SCK CPOL=1 MOSI MSB23. Package Diagrams Figure 23-1. 24-Pin 300-Mil SOIC S13Figure 23-2. 24-Pin 300-Mil PDIP P13 3. DIMENSIONS IN INCHESFigure 23-4. 28-Pin 5.3 mm Shrunk Small Outline Package O28 Figure 23-3. 24-Pin QSOP O241Page 65 of Figure 23-6. 48-Pin Shrunk Small Outline Package O48 Figure 23-5. 40-Pin 600-Mil Molded DIP P17Page 66 of 24. Document History Page Document NumberOrig. of SubmissionSales, Solutions, and Legal Information PSoC SolutionsWorldwide Sales and Design Support Products
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