Cypress CY7C602xx manual Absolute Maximum Ratings, DC Characteristics, Parameter, Conditions, Unit

Page 59
20. Absolute Maximum Ratings

 

 

 

 

 

CY7C601xx, CY7C602xx

 

 

 

 

 

 

 

 

 

 

 

20. Absolute Maximum Ratings

Maximum Total.............................................................Sink Output Current into Port 0

70 mA

Storage Temperature

 

–40°C to +90°C

and 1 and Pins

Maximum Total Source Output Current into GPIO Pins30 mA

Ambient Temperature with Power Applied

..... –0°C to +70°C

Maximum On-chip Power Dissipation

 

 

Supply Voltage on VCC Relative to VSS

–0.5V to +7.0V

on any GPIO Pin

50 mW

DC Input Voltage

–0.5V to + VCC + 0.5V

Power Dissipation

300 mW

DC Voltage Applied to Outputs in

 

 

Static Discharge Voltage

2200V

High-Z State

–0.5V to + VCC + 0.5V

Latch-up Current

200 mA

20.1 DC Characteristics

Parameter

Description

 

 

 

Conditions

 

Min

Typical

Max

Unit

General

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC1

Operating Voltage

CPU speed <= 12 MHz

 

2.7

 

3.6

V

TFP

Operating Temperature

Flash programming

 

 

0

 

70

°C

ICC1

VCC Operating Supply Current

CPU =12 MHz, Vdd = 3.3V, T = 75C

 

 

 

4.25

11

mA

 

 

 

CPU =12 MHz, Vdd = 2.7V, T = 25C

 

 

 

3.25

-

mA

 

 

 

 

 

 

 

 

 

ICC2

VCC Operating Supply Current

CPU = 6 MHz, Vdd = 3.3V, T = 75C

 

 

 

3.15

9

mA

 

 

 

CPU = 6 MHz, Vdd = 3.3V, T = 25C

 

 

 

2.45

-

mA

 

 

 

 

 

 

 

 

 

ICC3

VCC Operating Supply Current

CPU = 3 MHz, Vdd = 2.7V, T = 25C

 

 

 

2.0

-

mA

ISB1

Standby Current

Internal and external oscillators,

 

 

 

 

10

μA

 

 

 

Bandgap, Flash, CPU clock, timer

 

 

 

 

 

 

 

 

 

clock all disabled

 

 

 

 

 

 

Low Voltage

Detect

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VLVD

Low Voltage Detect Trip Voltage

LVDCR [2:0] set to 000

 

2.681

 

2.7

V

General Purpose IO Interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RUP

Pull Up Resistance

 

 

 

 

 

 

4

 

12

KΩ

VICR

Input Threshold Voltage Low, CMOS

Low to high edge

 

40%

 

65%

VCC

 

 

Mode

 

 

 

 

 

 

 

 

 

 

VICF

Input Threshold Voltage Low, CMOS

High to low edge

 

30%

 

55%

VCC

 

 

Mode

 

 

 

 

 

 

 

 

 

 

VHC

Input Hysteresis Voltage, CMOS Mode

High to low edge

 

3%

 

10%

VCC

VILTTL

Input Low Voltage, TTL Mode

 

 

 

 

 

 

 

 

0.72

V

VIHTTL

Input HIGH Voltage, TTL Mode

 

 

 

 

 

1.6

 

 

V

V

OL1

Output Low Voltage, High Drive[4]

I

OL1

= 50 mA

 

 

 

 

1.4

V

 

 

 

 

 

 

 

 

 

 

V

OL2

Output Low Voltage, High Drive[4]

I

OL1

= 25 mA

 

 

 

 

0.4

V

 

 

 

 

 

 

 

 

 

 

VOL3

Output Low Voltage, Low Drive

IOL2 = 8 mA

 

 

 

 

0.8

V

V

OH

Output High Voltage[4]

I

OH

= 2 mA

V

CC

– 0.5

 

 

V

 

 

 

 

 

 

 

 

 

 

Notes

5.Refer to Clocking on page 21 for details on loading proper trim values.

6.In Master mode first bit is available 0.5 SPICLK cycle before Master clock edge available on the SCLK pin.

Document 38-16016 Rev. *E

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Contents Cypress Semiconductor Corporation 1. Features2. Logic Block Diagram CY7C601xx, CY7C602xx5. Conventions 3. Applications4. Introduction 24-Pin PDIP Figure 6-1. Package Configurations Top View6. Pinouts CY7C60223Name CY7C601xx, CY7C602xx6.1 Pin Assignments Table 6-1. Pin AssignmentsTable 6-1. Pin Assignments continued Addr Default7. Register Summary Table 7-1. enCoRe II LV Register SummaryTable 7-1. enCoRe II LV Register Summary continued Table 8-1. CPU Registers and Register Name 8. CPU Architecture9. CPU Registers 9.1 Flags RegisterTable 9-3. CPU X Register CPUX 9.1.1 Accumulator RegisterTable 9-2. CPU Accumulator Register CPUA 9.1.2 Index RegisterOpcode 9.2 Addressing Modes9.2.1 Source Immediate Table 9-7. Source Immediate9.2.6 Destination Direct Source Immediate 9.2.5 Destination IndexedTable 9-11. Destination Indexed Example9.2.10 Destination Indirect Post Increment 10. Instruction Set Summary9.2.9 Source Indirect Post Increment Table 9-15. Source Indirect Post IncrementFlags 0x1FFF 11. Memory Organization11.1 Flash Program Memory Organization Figure 11-1. Program Memory Space with Interrupt Vector TableFigure 11-2. Data Memory Organization 11.2 Data Memory Organization11.3 Flash 11.4 SROMVariable Name 11.5.1 SWBootReset Function11.5 SROM Function Descriptions Table 11-2. SROM Function Parameters11.5.4 EraseBlock Function Settings11.5.3 WriteBlock Function Table 11-5. WriteBlock ParametersTable 11-10. Table Read Parameters Table 11-8. ProtectBlock Parameters11.5.6 EraseAll Function 11.5.7 TableRead FunctionPage 19 of 11.6 SROM Table Read Descriptioneg ti Gain value for the register at location 0x38 3.3V = Table 12-1. Oscillator Trim Values vs. Voltage Settings12. Clocking 12.1 Trim Values for the IOSCTR Register12.2.1 CPU Clock 12.2 Clock Architecture DescriptionTable 12-3. OSC Control 0 OSCCR0 0x1E0 R/W Figure 12-1. CPU Clock Block DiagramTable 12-2. CPU Clock Configuration CPUCLKCR 0x30 R/W Bit 71 ReservedTable 12-3. OSC Control 0 OSCCR0 0x1E0 R/W continued Sleep TimerSleep Timer Clock CPU when InternalBit 75 Reserved Table 12-4. Clock IO Configuration CLKIOCR 0x32 R/W12.2.2 Interval Timer Clock ITMRCLK Figure 12-3. Timer Capture Block Diagram Figure 12-2. Programmable Interval Timer Block Diagram12.2.3 Timer Capture Clock TCAPCLK Page 27 of Table 12-5. Timer Clock Configuration TMRCLKCR 0x31 R/WBit 40 Gain XGM Setting12.2.4 Internal Clock Trim Table 12-6. IOSC Trim IOSCTR 0x34 R/WTable 12-8. LPOSC Trim LPOSCTR 0x36 R/W 12.3 CPU Clock During Sleep Mode12.2.6 LPOSC Trim Bit 5 WDRS 13. ResetTable 13-1. System Status and Control Register CPUSCR 0xFF R/W Bit 7 GIES14. Sleep Mode 13.1 Power On Reset13.2 Watchdog Timer Reset Table 13-2. Reset Watchdog Timer RESWDT 0xE3 WFigure 14-1. Sleep Timing 14.1.1 Low Power in Sleep Mode14.1 Sleep Sequence CPUCLK IOW SLEEP BRQ BRA PDFigure 14-2. Wakeup Timing 14.2 Wakeup SequenceBit 20 VM20 15. Low Voltage Detect ControlTable 15-1. Low Voltage Control Register LVDCR 0x1E3 R/W Bit 76 Reserved Bit 54 PORLEV10Bit 72 Reserved Bit 1 LVD 15.1 POR Compare State15.2 ECO Trim Register Table 15-2. Voltage Monitor Comparators Register VLTCMP 0x1E4 RTable 16-1. P0 Data Register P0DATA0x00 R/W 16. General Purpose IO Ports16.1 Port Data Registers 16.1.1 P0 DataTable 16-3. P2 Data Register P2DATA 0x02 R/W 16.2 GPIO Port Configuration16.2.1 Int Enable 16.1.3 P2 Data16.2.9 P0.0/CLKIN Configuration 16.2.7 Output Enable16.2.6 Pull Up Enable Figure 16-1. GPIO Block Diagram16.2.11 P0.2/INT0-P0.4/INT2 Configuration 16.2.10 P0.1/CLKOUT ConfigurationTable 16-7. P0.1/CLKOUT Configuration P01CR 0x06 R/W 16.2.14 P1.0 Configuration 16.2.12 P0.5/TIO0-P0.6/TIO1 Configuration16.2.13 P0.7 Configuration Table 16-10. P0.7 Configuration P07CR 0x0C R/WTable 16-13. P1.2 Configuration P12CR 0x0F R/W 16.2.15 P1.1 ConfigurationTable 16-12. P1.1 Configuration P11CR 0x0E R/W 16.2.16 P1.2 ConfigurationTable 16-16. P1.7 Configuration P17CR 0x14 R/W 16.2.18 P1.4-P1.6 Configuration SCLK, SMOSI, SMISOTable 16-15. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W 16.2.19 P1.7 ConfigurationTable 16-19. P4 Configuration P4CR 0x17 R/W 16.2.21 P3 ConfigurationTable 16-18. P3 Configuration P3CR 0x16 R/W 16.2.22 P4 Configuration17. Serial Peripheral Interface SPI Figure 17-1. SPI Block DiagramTable 17-1. SPI Data Register SPIDATA 0x3C R/W 17.2 SPI Configure RegisterTable 17-2. SPI Configure Register SPICR 0x3D R/W 17.1 SPI Data RegisterCPOL Table 17-3. SPI Mode Timing vs. LSB First, CPOL, and CPHADiagram CPHATable 18-1. Free Running Timer Low Order Byte FRTMRL 0x20 R/W 18. Timer Registers17.3 SPI Interface Pins Figure 18-1. 16-Bit Free Running Counter Block Diagram18.1.2 Time Capture Table 18-2. Free Running Timer High Order Byte FRTMRH 0x21 R/WFigure 18-2. Time Capture Block Diagram Table 18-3. Timer Configuration TMRCR 0x2A R/WTable 18-7. Timer Capture 0 Falling TCAP0F 0x24 R/W Table 18-4. Capture Interrupt Enable TCAPINTE 0x2B R/WTable 18-5. Timer Capture 0 Rising TCAP0R 0x22 R/W Table 18-6. Timer Capture 1 Rising TCAP1R 0x23 R/WTable 18-9. Capture Interrupt Status TCAPINTS 0x2C R/W Table 18-8. Timer Capture 1 Falling TCAP1F 0x25 R/W18.1.3 Programmable Interval Timer Table 18-10. Programmable Interval Timer Low PITMRL 0x26 RTable 18-13. Programmable Interval Reload High PIRH 0x29 R/W Table 18-11. Programmable Interval Timer High PITMRH 0x27 RTable 18-12. Programmable Interval Reload Low PIRL 0x28 R/W Page 52 of Figure 18-3. Timer Functional Sequence DiagramFigure 18-5. Memory Mapped Registers Read and Write Timing Diagram Figure 18-4. 16-Bit Free Running Counter Loading Timing DiagramTable 19-1. Interrupt Priorities, Address, and Name Figure 19-1. Interrupt Controller Block Diagram19. Interrupt Controller 19.1 Architectural DescriptionTable 19-2. Interrupt Clear 0 INTCLR0 0xDA R/W 19.2 Interrupt Processing19.3 Interrupt Latency 19.4 Interrupt RegistersTable 19-5. Interrupt Mask 3 INTMSK3 0xDE R/W Table 19-3. Interrupt Clear 1 INTCLR1 0xDB R/WInterrupt Clear 2 INTCLR2 0xDC R/W 19.4.2 Interrupt Mask RegistersPage 57 of Table 19-6. Interrupt Mask 2 INTMSK2 0xDF R/WTable 19-7. Interrupt Mask 1 INTMSK1 0xE1 R/W Table 19-9. Interrupt Vector Clear Register INTVC 0xE2 R/W Table 19-8. Interrupt Mask 0 INTMSK0 0xE0 R/W19.4.3 Interrupt Vector Clear Register Conditions 20.1 DC Characteristics20. Absolute Maximum Ratings ParameterFigure 20-1. Clock Timing 20.2 AC CharacteristicsClock SPI TimingMOSI MISO Figure 20-2. GPIO Timing DiagramSCK CPOL=0 SCK CPOL=1MOSI MISO MSB MOSIMISO SS SCK CPOL=0 SCK CPOL=1MOSI MSB 21. Ordering Information22. Package Handling SCK CPOL=0 SCK CPOL=13. DIMENSIONS IN INCHES 23. Package DiagramsFigure 23-1. 24-Pin 300-Mil SOIC S13 Figure 23-2. 24-Pin 300-Mil PDIP P13Page 65 of Figure 23-3. 24-Pin QSOP O241Figure 23-4. 28-Pin 5.3 mm Shrunk Small Outline Package O28 Page 66 of Figure 23-5. 40-Pin 600-Mil Molded DIP P17Figure 23-6. 48-Pin Shrunk Small Outline Package O48 Submission 24. Document History PageDocument Number Orig. ofProducts Sales, Solutions, and Legal InformationPSoC Solutions Worldwide Sales and Design Support
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