Cypress Interrupt Controller, Architectural Description, Priority, CY7C601xx, CY7C602xx, Name

Page 54
19. Interrupt Controller

CY7C601xx, CY7C602xx

19. Interrupt Controller

The interrupt controller and its associated registers allow the user’s code to respond to an interrupt from almost every functional block in the enCoRe II LV devices. The registers associated with the interrupt controller are disabled either globally or individually. The registers also provide a mechanism for users to clear all pending and posted interrupts or clear individual posted or pending interrupts.

Table 19-1lists all interrupts and the priorities that are available in the enCoRe II LV devices.

Table 19-1. Interrupt Priorities, Address, and Name

Interrupt

Interrupt

Name

Priority

Address

 

0

0000h

Reset

 

 

 

1

0004h

POR/LVD

 

 

 

2

0008h

INT0

 

 

 

3

000Ch

SPI Transmitter Empty

 

 

 

4

0010h

SPI Receiver Full

 

 

 

5

0014h

GPIO Port 0

 

 

 

6

0018h

GPIO Port 1

 

 

 

7

001Ch

INT1

 

 

 

8

0020h

Reserved

 

 

 

9

0024h

Reserved

 

 

 

10

0028h

Reserved

 

 

 

11

002Ch

Reserved

 

 

 

12

0030h

Reserved

 

 

 

13

0034h

1 mS Interval timer

 

 

 

14

0038h

Programmable Interval Timer

 

 

 

15

003Ch

Timer Capture 0

 

 

 

Table 19-1. Interrupt Priorities, Address, and Name (contin-

Interrupt

Interrupt

Name

Priority

Address

 

 

 

 

160040h Timer Capture 1

170044h 16-bit Free Running Timer Wrap

180048h INT2

19004Ch Reserved

200050h GPIO Port 2

210054h GPIO Port 3

220058h GPIO Port 4

23005Ch Reserved

240060h Reserved

250064h Sleep Timer

19.1Architectural Description

An interrupt is posted when its interrupt conditions occur. This results in the flip-flop in Figure 19-1.clocking in a ‘1’. The interrupt remains posted until the interrupt is taken or until it is cleared by writing to the appropriate INT_CLRx register.

A posted interrupt is not pending unless it is enabled by setting its interrupt mask bit (in the appropriate INT_MSKx register). All pending interrupts are processed by the Priority Encoder to determine the highest priority interrupt which is taken by the M8C if the Global Interrupt Enable bit is set in the CPU_F register.

Disabling an interrupt by clearing its interrupt mask bit (in the INT_MSKx register) does not clear a posted interrupt, nor does it prevent an interrupt from being posted. It simply prevents a posted interrupt from becoming pending.

Nested interrupts are accomplished by reenabling interrupts inside an interrupt service routine. To do this, set the IE bit in the Flag Register. A block diagram of the enCoRe II LV Interrupt Controller is shown in Figure 19-1..

Figure 19-1. Interrupt Controller Block Diagram

Interrupt

Source

(Timer,

GPIO,etc.)

 

InterruptTaken

Priority

 

Encoder

 

or

 

 

 

INT_CLRxWrite

 

 

Posted

Pending

 

Interrupt

Interrupt

 

R

...

1

D Q

...

 

 

INT_MSKx

Mask Bit Setting

Table 19-1. Interrupt Priorities, Address, and Name Interrupt Vector

CPU_F[0]

GIE

Interrupt

Request

M8C Core

Document 38-16016 Rev. *E

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Contents CY7C601xx, CY7C602xx 1. Features2. Logic Block Diagram Cypress Semiconductor Corporation3. Applications 4. Introduction5. Conventions CY7C60223 Figure 6-1. Package Configurations Top View6. Pinouts 24-Pin PDIPTable 6-1. Pin Assignments CY7C601xx, CY7C602xx6.1 Pin Assignments NameTable 6-1. Pin Assignments continued Table 7-1. enCoRe II LV Register Summary Default7. Register Summary AddrTable 7-1. enCoRe II LV Register Summary continued 9.1 Flags Register 8. CPU Architecture9. CPU Registers Table 8-1. CPU Registers and Register Name9.1.2 Index Register 9.1.1 Accumulator RegisterTable 9-2. CPU Accumulator Register CPUA Table 9-3. CPU X Register CPUXTable 9-7. Source Immediate 9.2 Addressing Modes9.2.1 Source Immediate OpcodeExample 9.2.5 Destination IndexedTable 9-11. Destination Indexed 9.2.6 Destination Direct Source ImmediateTable 9-15. Source Indirect Post Increment 10. Instruction Set Summary9.2.9 Source Indirect Post Increment 9.2.10 Destination Indirect Post IncrementBytes Figure 11-1. Program Memory Space with Interrupt Vector Table 11. Memory Organization11.1 Flash Program Memory Organization 0x1FFF11.4 SROM 11.2 Data Memory Organization11.3 Flash Figure 11-2. Data Memory OrganizationTable 11-2. SROM Function Parameters 11.5.1 SWBootReset Function11.5 SROM Function Descriptions Variable NameTable 11-5. WriteBlock Parameters Settings11.5.3 WriteBlock Function 11.5.4 EraseBlock Function11.5.7 TableRead Function Table 11-8. ProtectBlock Parameters11.5.6 EraseAll Function Table 11-10. Table Read Parameters11.6 SROM Table Read Description Page 19 ofeg ti 12.1 Trim Values for the IOSCTR Register Table 12-1. Oscillator Trim Values vs. Voltage Settings12. Clocking Gain value for the register at location 0x38 3.3V =12.2 Clock Architecture Description 12.2.1 CPU ClockBit 71 Reserved Figure 12-1. CPU Clock Block DiagramTable 12-2. CPU Clock Configuration CPUCLKCR 0x30 R/W Table 12-3. OSC Control 0 OSCCR0 0x1E0 R/WCPU when Internal Sleep TimerSleep Timer Clock Table 12-3. OSC Control 0 OSCCR0 0x1E0 R/W continuedTable 12-4. Clock IO Configuration CLKIOCR 0x32 R/W 12.2.2 Interval Timer Clock ITMRCLKBit 75 Reserved Figure 12-2. Programmable Interval Timer Block Diagram 12.2.3 Timer Capture Clock TCAPCLKFigure 12-3. Timer Capture Block Diagram Table 12-5. Timer Clock Configuration TMRCLKCR 0x31 R/W Page 27 ofTable 12-6. IOSC Trim IOSCTR 0x34 R/W XGM Setting12.2.4 Internal Clock Trim Bit 40 Gain12.3 CPU Clock During Sleep Mode 12.2.6 LPOSC TrimTable 12-8. LPOSC Trim LPOSCTR 0x36 R/W Bit 7 GIES 13. ResetTable 13-1. System Status and Control Register CPUSCR 0xFF R/W Bit 5 WDRSTable 13-2. Reset Watchdog Timer RESWDT 0xE3 W 13.1 Power On Reset13.2 Watchdog Timer Reset 14. Sleep ModeCPUCLK IOW SLEEP BRQ BRA PD 14.1.1 Low Power in Sleep Mode14.1 Sleep Sequence Figure 14-1. Sleep Timing14.2 Wakeup Sequence Figure 14-2. Wakeup TimingBit 76 Reserved Bit 54 PORLEV10 15. Low Voltage Detect ControlTable 15-1. Low Voltage Control Register LVDCR 0x1E3 R/W Bit 20 VM20Table 15-2. Voltage Monitor Comparators Register VLTCMP 0x1E4 R 15.1 POR Compare State15.2 ECO Trim Register Bit 72 Reserved Bit 1 LVD16.1.1 P0 Data 16. General Purpose IO Ports16.1 Port Data Registers Table 16-1. P0 Data Register P0DATA0x00 R/W16.1.3 P2 Data 16.2 GPIO Port Configuration16.2.1 Int Enable Table 16-3. P2 Data Register P2DATA 0x02 R/WFigure 16-1. GPIO Block Diagram 16.2.7 Output Enable16.2.6 Pull Up Enable 16.2.9 P0.0/CLKIN Configuration16.2.10 P0.1/CLKOUT Configuration Table 16-7. P0.1/CLKOUT Configuration P01CR 0x06 R/W16.2.11 P0.2/INT0-P0.4/INT2 Configuration Table 16-10. P0.7 Configuration P07CR 0x0C R/W 16.2.12 P0.5/TIO0-P0.6/TIO1 Configuration16.2.13 P0.7 Configuration 16.2.14 P1.0 Configuration16.2.16 P1.2 Configuration 16.2.15 P1.1 ConfigurationTable 16-12. P1.1 Configuration P11CR 0x0E R/W Table 16-13. P1.2 Configuration P12CR 0x0F R/W16.2.19 P1.7 Configuration 16.2.18 P1.4-P1.6 Configuration SCLK, SMOSI, SMISOTable 16-15. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W Table 16-16. P1.7 Configuration P17CR 0x14 R/W16.2.22 P4 Configuration 16.2.21 P3 ConfigurationTable 16-18. P3 Configuration P3CR 0x16 R/W Table 16-19. P4 Configuration P4CR 0x17 R/WFigure 17-1. SPI Block Diagram 17. Serial Peripheral Interface SPI17.1 SPI Data Register 17.2 SPI Configure RegisterTable 17-2. SPI Configure Register SPICR 0x3D R/W Table 17-1. SPI Data Register SPIDATA 0x3C R/WCPHA Table 17-3. SPI Mode Timing vs. LSB First, CPOL, and CPHADiagram CPOLFigure 18-1. 16-Bit Free Running Counter Block Diagram 18. Timer Registers17.3 SPI Interface Pins Table 18-1. Free Running Timer Low Order Byte FRTMRL 0x20 R/WTable 18-3. Timer Configuration TMRCR 0x2A R/W Table 18-2. Free Running Timer High Order Byte FRTMRH 0x21 R/WFigure 18-2. Time Capture Block Diagram 18.1.2 Time CaptureTable 18-6. Timer Capture 1 Rising TCAP1R 0x23 R/W Table 18-4. Capture Interrupt Enable TCAPINTE 0x2B R/WTable 18-5. Timer Capture 0 Rising TCAP0R 0x22 R/W Table 18-7. Timer Capture 0 Falling TCAP0F 0x24 R/WTable 18-10. Programmable Interval Timer Low PITMRL 0x26 R Table 18-8. Timer Capture 1 Falling TCAP1F 0x25 R/W18.1.3 Programmable Interval Timer Table 18-9. Capture Interrupt Status TCAPINTS 0x2C R/WTable 18-11. Programmable Interval Timer High PITMRH 0x27 R Table 18-12. Programmable Interval Reload Low PIRL 0x28 R/WTable 18-13. Programmable Interval Reload High PIRH 0x29 R/W Figure 18-3. Timer Functional Sequence Diagram Page 52 ofFigure 18-4. 16-Bit Free Running Counter Loading Timing Diagram Figure 18-5. Memory Mapped Registers Read and Write Timing Diagram19.1 Architectural Description Figure 19-1. Interrupt Controller Block Diagram19. Interrupt Controller Table 19-1. Interrupt Priorities, Address, and Name19.4 Interrupt Registers 19.2 Interrupt Processing19.3 Interrupt Latency Table 19-2. Interrupt Clear 0 INTCLR0 0xDA R/W19.4.2 Interrupt Mask Registers Table 19-3. Interrupt Clear 1 INTCLR1 0xDB R/WInterrupt Clear 2 INTCLR2 0xDC R/W Table 19-5. Interrupt Mask 3 INTMSK3 0xDE R/WTable 19-6. Interrupt Mask 2 INTMSK2 0xDF R/W Table 19-7. Interrupt Mask 1 INTMSK1 0xE1 R/WPage 57 of Table 19-8. Interrupt Mask 0 INTMSK0 0xE0 R/W 19.4.3 Interrupt Vector Clear RegisterTable 19-9. Interrupt Vector Clear Register INTVC 0xE2 R/W Parameter 20.1 DC Characteristics20. Absolute Maximum Ratings ConditionsSPI Timing 20.2 AC CharacteristicsClock Figure 20-1. Clock TimingSCK CPOL=1 Figure 20-2. GPIO Timing DiagramSCK CPOL=0 MOSI MISOSS SCK CPOL=0 SCK CPOL=1 MOSIMISO MOSI MISO MSBSCK CPOL=0 SCK CPOL=1 21. Ordering Information22. Package Handling MOSI MSBFigure 23-2. 24-Pin 300-Mil PDIP P13 23. Package DiagramsFigure 23-1. 24-Pin 300-Mil SOIC S13 3. DIMENSIONS IN INCHESFigure 23-3. 24-Pin QSOP O241 Figure 23-4. 28-Pin 5.3 mm Shrunk Small Outline Package O28Page 65 of Figure 23-5. 40-Pin 600-Mil Molded DIP P17 Figure 23-6. 48-Pin Shrunk Small Outline Package O48Page 66 of Orig. of 24. Document History PageDocument Number SubmissionWorldwide Sales and Design Support Sales, Solutions, and Legal InformationPSoC Solutions Products
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