Cypress CY7C602xx, CY7C601xx manual Interrupt Processing, Interrupt Latency, Interrupt Registers

Page 55
19.2 Interrupt Processing

CY7C601xx, CY7C602xx

19.2 Interrupt Processing

The sequence of events that occur during interrupt processing is as follows:

1.An interrupt becomes active, either because:

a.The interrupt condition occurs (for example, a timer expires).

b.A previously posted interrupt is enabled through an update of an interrupt mask register.

c.An interrupt is pending and GIE is set from 0 to 1 in the CPU Flag register.

2.The current executing instruction finishes.

3.The internal interrupt is dispatched, taking 13 cycles. During this time, the following actions occur:

a.The MSB and LSB of Program Counter and Flag registers (CPU_PC and CPU_F) are stored onto the program stack by an automatic CALL instruction (13 cycles) generated during the interrupt acknowledge process.

b.The PCH, PCL, and Flag register (CPU_F) are stored onto the program stack (in that order) by an automatic CALL instruction (13 cycles) generated during the interrupt acknowledge process.

c.The CPU_F register is then cleared. Since this clears the GIE bit to 0, additional interrupts are temporarily disabled.

d.The PCH (PC[15:8]) is cleared to zero.

e.The interrupt vector is read from the interrupt controller and its value placed into PCL (PC[7:0]). This sets the program counter to point to the appropriate address in the interrupt table (for example, 0004h for the POR and LVD interrupt).

4.Program execution vectors to the interrupt table. Typically, a LJMP instruction in the interrupt table sends execution to the user's Interrupt Service Routine (ISR) for this interrupt.

5.The ISR executes. Note that interrupts are disabled since

GIE = 0. In the ISR, interrupts are re-enabled if desired, by setting GIE = 1 (avoid stack overflow).

Table 19-2. Interrupt Clear 0 (INT_CLR0) [0xDA] [R/W]

6.The ISR ends with a RETI instruction which restores the Program Counter and Flag registers (CPU_PC and CPU_F). The restored Flag register re-enables interrupts, since GIE = 1 again.

7.Execution resumes at the next instruction, after the one that occurred before the interrupt. However, if there are more pending interrupts, the subsequent interrupts are processed before the next normal program instruction.

19.3 Interrupt Latency

The time between the assertion of an enabled interrupt and the start of its ISR is calculated from the following equation.

Latency = Time for current instruction to finish + Time for internal interrupt routine to execute + Time for LJMP instruction in interrupt table to execute.

For example, if the 5 cycle JMP instruction is executing when an interrupt becomes active, the total number of CPU clock cycles before the ISR begins is as follows:

(1 to 5 cycles for JMP to finish) + (13 cycles for interrupt routine) + (7 cycles for LJMP) = 21 to 25 cycles.

In the example above, at 12 MHz, 25 clock cycles take 2.08 µs.

19.4 Interrupt Registers

19.4.1 Interrupt Clear Register

The Interrupt Clear Registers (INT_CLRx) are used to enable the individual interrupt sources’ ability to clear posted interrupts.

When an INT_CLRx register is read, any bits that are set indicates an interrupt has been posted for that hardware resource. Therefore, reading these registers gives the user the ability to determine all posted interrupts.

Bit #

7

6

5

4

3

2

1

0

Field

GPIO Port 1

Sleep Timer

INT1

GPIO Port 0

SPI Receive

SPI Transmit

INT0

POR/LVD

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Default

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

When reading this register,

0 = There is no posted interrupt for the corresponding hardware.

1 = There is a posted interrupt for the corresponding hardware.

Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits and to the ENSWINT (Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt.

The GPIO interrupts are edge-triggered.

Document 38-16016 Rev. *E

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Contents Cypress Semiconductor Corporation 1. Features2. Logic Block Diagram CY7C601xx, CY7C602xx4. Introduction 3. Applications5. Conventions 24-Pin PDIP Figure 6-1. Package Configurations Top View6. Pinouts CY7C60223Name CY7C601xx, CY7C602xx6.1 Pin Assignments Table 6-1. Pin AssignmentsTable 6-1. Pin Assignments continued Addr Default7. Register Summary Table 7-1. enCoRe II LV Register SummaryTable 7-1. enCoRe II LV Register Summary continued Table 8-1. CPU Registers and Register Name 8. CPU Architecture9. CPU Registers 9.1 Flags RegisterTable 9-3. CPU X Register CPUX 9.1.1 Accumulator RegisterTable 9-2. CPU Accumulator Register CPUA 9.1.2 Index RegisterOpcode 9.2 Addressing Modes9.2.1 Source Immediate Table 9-7. Source Immediate9.2.6 Destination Direct Source Immediate 9.2.5 Destination IndexedTable 9-11. Destination Indexed Example9.2.10 Destination Indirect Post Increment 10. Instruction Set Summary9.2.9 Source Indirect Post Increment Table 9-15. Source Indirect Post IncrementFlags 0x1FFF 11. Memory Organization11.1 Flash Program Memory Organization Figure 11-1. Program Memory Space with Interrupt Vector TableFigure 11-2. Data Memory Organization 11.2 Data Memory Organization11.3 Flash 11.4 SROMVariable Name 11.5.1 SWBootReset Function11.5 SROM Function Descriptions Table 11-2. SROM Function Parameters11.5.4 EraseBlock Function Settings11.5.3 WriteBlock Function Table 11-5. WriteBlock ParametersTable 11-10. Table Read Parameters Table 11-8. ProtectBlock Parameters11.5.6 EraseAll Function 11.5.7 TableRead FunctionPage 19 of 11.6 SROM Table Read Descriptioneg ti Gain value for the register at location 0x38 3.3V = Table 12-1. Oscillator Trim Values vs. Voltage Settings12. Clocking 12.1 Trim Values for the IOSCTR Register12.2.1 CPU Clock 12.2 Clock Architecture DescriptionTable 12-3. OSC Control 0 OSCCR0 0x1E0 R/W Figure 12-1. CPU Clock Block DiagramTable 12-2. CPU Clock Configuration CPUCLKCR 0x30 R/W Bit 71 ReservedTable 12-3. OSC Control 0 OSCCR0 0x1E0 R/W continued Sleep TimerSleep Timer Clock CPU when Internal12.2.2 Interval Timer Clock ITMRCLK Table 12-4. Clock IO Configuration CLKIOCR 0x32 R/WBit 75 Reserved 12.2.3 Timer Capture Clock TCAPCLK Figure 12-2. Programmable Interval Timer Block DiagramFigure 12-3. Timer Capture Block Diagram Page 27 of Table 12-5. Timer Clock Configuration TMRCLKCR 0x31 R/WBit 40 Gain XGM Setting12.2.4 Internal Clock Trim Table 12-6. IOSC Trim IOSCTR 0x34 R/W12.2.6 LPOSC Trim 12.3 CPU Clock During Sleep ModeTable 12-8. LPOSC Trim LPOSCTR 0x36 R/W Bit 5 WDRS 13. ResetTable 13-1. System Status and Control Register CPUSCR 0xFF R/W Bit 7 GIES14. Sleep Mode 13.1 Power On Reset13.2 Watchdog Timer Reset Table 13-2. Reset Watchdog Timer RESWDT 0xE3 WFigure 14-1. Sleep Timing 14.1.1 Low Power in Sleep Mode14.1 Sleep Sequence CPUCLK IOW SLEEP BRQ BRA PDFigure 14-2. Wakeup Timing 14.2 Wakeup SequenceBit 20 VM20 15. Low Voltage Detect ControlTable 15-1. Low Voltage Control Register LVDCR 0x1E3 R/W Bit 76 Reserved Bit 54 PORLEV10Bit 72 Reserved Bit 1 LVD 15.1 POR Compare State15.2 ECO Trim Register Table 15-2. Voltage Monitor Comparators Register VLTCMP 0x1E4 RTable 16-1. P0 Data Register P0DATA0x00 R/W 16. General Purpose IO Ports16.1 Port Data Registers 16.1.1 P0 DataTable 16-3. P2 Data Register P2DATA 0x02 R/W 16.2 GPIO Port Configuration16.2.1 Int Enable 16.1.3 P2 Data16.2.9 P0.0/CLKIN Configuration 16.2.7 Output Enable16.2.6 Pull Up Enable Figure 16-1. GPIO Block DiagramTable 16-7. P0.1/CLKOUT Configuration P01CR 0x06 R/W 16.2.10 P0.1/CLKOUT Configuration16.2.11 P0.2/INT0-P0.4/INT2 Configuration 16.2.14 P1.0 Configuration 16.2.12 P0.5/TIO0-P0.6/TIO1 Configuration16.2.13 P0.7 Configuration Table 16-10. P0.7 Configuration P07CR 0x0C R/WTable 16-13. P1.2 Configuration P12CR 0x0F R/W 16.2.15 P1.1 ConfigurationTable 16-12. P1.1 Configuration P11CR 0x0E R/W 16.2.16 P1.2 ConfigurationTable 16-16. P1.7 Configuration P17CR 0x14 R/W 16.2.18 P1.4-P1.6 Configuration SCLK, SMOSI, SMISOTable 16-15. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W 16.2.19 P1.7 ConfigurationTable 16-19. P4 Configuration P4CR 0x17 R/W 16.2.21 P3 ConfigurationTable 16-18. P3 Configuration P3CR 0x16 R/W 16.2.22 P4 Configuration17. Serial Peripheral Interface SPI Figure 17-1. SPI Block DiagramTable 17-1. SPI Data Register SPIDATA 0x3C R/W 17.2 SPI Configure RegisterTable 17-2. SPI Configure Register SPICR 0x3D R/W 17.1 SPI Data RegisterCPOL Table 17-3. SPI Mode Timing vs. LSB First, CPOL, and CPHADiagram CPHATable 18-1. Free Running Timer Low Order Byte FRTMRL 0x20 R/W 18. Timer Registers17.3 SPI Interface Pins Figure 18-1. 16-Bit Free Running Counter Block Diagram18.1.2 Time Capture Table 18-2. Free Running Timer High Order Byte FRTMRH 0x21 R/WFigure 18-2. Time Capture Block Diagram Table 18-3. Timer Configuration TMRCR 0x2A R/WTable 18-7. Timer Capture 0 Falling TCAP0F 0x24 R/W Table 18-4. Capture Interrupt Enable TCAPINTE 0x2B R/WTable 18-5. Timer Capture 0 Rising TCAP0R 0x22 R/W Table 18-6. Timer Capture 1 Rising TCAP1R 0x23 R/WTable 18-9. Capture Interrupt Status TCAPINTS 0x2C R/W Table 18-8. Timer Capture 1 Falling TCAP1F 0x25 R/W18.1.3 Programmable Interval Timer Table 18-10. Programmable Interval Timer Low PITMRL 0x26 RTable 18-12. Programmable Interval Reload Low PIRL 0x28 R/W Table 18-11. Programmable Interval Timer High PITMRH 0x27 RTable 18-13. Programmable Interval Reload High PIRH 0x29 R/W Page 52 of Figure 18-3. Timer Functional Sequence DiagramFigure 18-5. Memory Mapped Registers Read and Write Timing Diagram Figure 18-4. 16-Bit Free Running Counter Loading Timing DiagramTable 19-1. Interrupt Priorities, Address, and Name Figure 19-1. Interrupt Controller Block Diagram19. Interrupt Controller 19.1 Architectural DescriptionTable 19-2. Interrupt Clear 0 INTCLR0 0xDA R/W 19.2 Interrupt Processing19.3 Interrupt Latency 19.4 Interrupt RegistersTable 19-5. Interrupt Mask 3 INTMSK3 0xDE R/W Table 19-3. Interrupt Clear 1 INTCLR1 0xDB R/WInterrupt Clear 2 INTCLR2 0xDC R/W 19.4.2 Interrupt Mask RegistersTable 19-7. Interrupt Mask 1 INTMSK1 0xE1 R/W Table 19-6. Interrupt Mask 2 INTMSK2 0xDF R/WPage 57 of 19.4.3 Interrupt Vector Clear Register Table 19-8. Interrupt Mask 0 INTMSK0 0xE0 R/WTable 19-9. Interrupt Vector Clear Register INTVC 0xE2 R/W Conditions 20.1 DC Characteristics20. Absolute Maximum Ratings ParameterFigure 20-1. Clock Timing 20.2 AC CharacteristicsClock SPI TimingMOSI MISO Figure 20-2. GPIO Timing DiagramSCK CPOL=0 SCK CPOL=1MOSI MISO MSB MOSIMISO SS SCK CPOL=0 SCK CPOL=1MOSI MSB 21. Ordering Information22. Package Handling SCK CPOL=0 SCK CPOL=13. DIMENSIONS IN INCHES 23. Package DiagramsFigure 23-1. 24-Pin 300-Mil SOIC S13 Figure 23-2. 24-Pin 300-Mil PDIP P13Figure 23-4. 28-Pin 5.3 mm Shrunk Small Outline Package O28 Figure 23-3. 24-Pin QSOP O241Page 65 of Figure 23-6. 48-Pin Shrunk Small Outline Package O48 Figure 23-5. 40-Pin 600-Mil Molded DIP P17Page 66 of Submission 24. Document History PageDocument Number Orig. ofProducts Sales, Solutions, and Legal InformationPSoC Solutions Worldwide Sales and Design Support
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