Cypress manual Wakeup Sequence, 2. Wakeup Timing, CY7C601xx, CY7C602xx

Page 33
14.2 Wakeup Sequence

CY7C601xx, CY7C602xx

14.2 Wakeup Sequence

When asleep, the only event that wakes the system up is an interrupt. The global interrupt enable of the CPU flag register need not be set. Any unmasked interrupt wakes the system up. It is optional for the CPU to actually take the interrupt after the wakeup sequence. The wakeup sequence is synchronized to the 32 kHz clock for purposes of sequencing a startup delay, to allow the Flash memory module enough time to power up before the CPU asserts the first read access. Another reason for the delay is to allow the oscillator, Bandgap, and LVD and POR circuits time to settle before actually being used in the system. As shown in Figure 14-2., the wakeup sequence is as follows:

1.The wakeup interrupt occurs and is synchronized by the neg- ative edge of the 32 kHz clock.

2.At the following positive edge of the 32 kHz clock, the system wide PD signal is negated. The Flash memory module,

internal oscillator, EFTB, and bandgap circuit are all powered up to a normal operating state.

3.At the following positive edge of the 32 kHz clock, the current values for the precision POR and LVD have settled and are sampled.

4.At the following negative edge of the 32 kHz clock (after about 15 µs nominal), the BRQ signal is negated by the sleep logic circuit. On the following CPUCLK, BRA is negated by the CPU and instruction execution resumes. Note that in Figure 14-2.fixed function blocks, such as Flash, internal oscillator, EFTB, and bandgap, have about 15 µs start up. The wakeup times (interrupt to CPU operational) range from 75 µs to 105 µs.

 

Figure 14-2. Wakeup Timing

 

Sleep Timer or GPIO

Interrupt is double sampled by

CPU is restarted after

32K clock and PD is negated to

interrupt occurs

 

90ms (nominal)

 

system

 

 

 

CLK32K

INT

SLEEP

PD

BANDGAP

ENABLE

SAMPLE

SAMPLE LVD/

 

 

 

 

 

 

POR

 

 

 

 

 

 

 

CPUCLK/

(Not to Scale)

 

 

 

24MHz

 

 

 

BRQ

 

 

 

 

 

 

 

 

 

 

 

 

BRA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document 38-16016 Rev. *E

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Contents 2. Logic Block Diagram 1. FeaturesCY7C601xx, CY7C602xx Cypress Semiconductor Corporation3. Applications 4. Introduction5. Conventions 6. Pinouts Figure 6-1. Package Configurations Top ViewCY7C60223 24-Pin PDIP6.1 Pin Assignments CY7C601xx, CY7C602xxTable 6-1. Pin Assignments NameTable 6-1. Pin Assignments continued 7. Register Summary DefaultTable 7-1. enCoRe II LV Register Summary AddrTable 7-1. enCoRe II LV Register Summary continued 9. CPU Registers 8. CPU Architecture9.1 Flags Register Table 8-1. CPU Registers and Register NameTable 9-2. CPU Accumulator Register CPUA 9.1.1 Accumulator Register9.1.2 Index Register Table 9-3. CPU X Register CPUX9.2.1 Source Immediate 9.2 Addressing ModesTable 9-7. Source Immediate OpcodeTable 9-11. Destination Indexed 9.2.5 Destination IndexedExample 9.2.6 Destination Direct Source Immediate9.2.9 Source Indirect Post Increment 10. Instruction Set SummaryTable 9-15. Source Indirect Post Increment 9.2.10 Destination Indirect Post IncrementCycles 11.1 Flash Program Memory Organization 11. Memory OrganizationFigure 11-1. Program Memory Space with Interrupt Vector Table 0x1FFF11.3 Flash 11.2 Data Memory Organization11.4 SROM Figure 11-2. Data Memory Organization11.5 SROM Function Descriptions 11.5.1 SWBootReset FunctionTable 11-2. SROM Function Parameters Variable Name11.5.3 WriteBlock Function SettingsTable 11-5. WriteBlock Parameters 11.5.4 EraseBlock Function11.5.6 EraseAll Function Table 11-8. ProtectBlock Parameters11.5.7 TableRead Function Table 11-10. Table Read ParametersPage 19 of 11.6 SROM Table Read Descriptioneg ti 12. Clocking Table 12-1. Oscillator Trim Values vs. Voltage Settings12.1 Trim Values for the IOSCTR Register Gain value for the register at location 0x38 3.3V =12.2.1 CPU Clock 12.2 Clock Architecture DescriptionTable 12-2. CPU Clock Configuration CPUCLKCR 0x30 R/W Figure 12-1. CPU Clock Block DiagramBit 71 Reserved Table 12-3. OSC Control 0 OSCCR0 0x1E0 R/WSleep Timer Clock Sleep TimerCPU when Internal Table 12-3. OSC Control 0 OSCCR0 0x1E0 R/W continuedTable 12-4. Clock IO Configuration CLKIOCR 0x32 R/W 12.2.2 Interval Timer Clock ITMRCLKBit 75 Reserved Figure 12-2. Programmable Interval Timer Block Diagram 12.2.3 Timer Capture Clock TCAPCLKFigure 12-3. Timer Capture Block Diagram Page 27 of Table 12-5. Timer Clock Configuration TMRCLKCR 0x31 R/W12.2.4 Internal Clock Trim XGM SettingTable 12-6. IOSC Trim IOSCTR 0x34 R/W Bit 40 Gain12.3 CPU Clock During Sleep Mode 12.2.6 LPOSC TrimTable 12-8. LPOSC Trim LPOSCTR 0x36 R/W Table 13-1. System Status and Control Register CPUSCR 0xFF R/W 13. ResetBit 7 GIES Bit 5 WDRS13.2 Watchdog Timer Reset 13.1 Power On ResetTable 13-2. Reset Watchdog Timer RESWDT 0xE3 W 14. Sleep Mode14.1 Sleep Sequence 14.1.1 Low Power in Sleep ModeCPUCLK IOW SLEEP BRQ BRA PD Figure 14-1. Sleep TimingFigure 14-2. Wakeup Timing 14.2 Wakeup SequenceTable 15-1. Low Voltage Control Register LVDCR 0x1E3 R/W 15. Low Voltage Detect ControlBit 76 Reserved Bit 54 PORLEV10 Bit 20 VM2015.2 ECO Trim Register 15.1 POR Compare StateTable 15-2. Voltage Monitor Comparators Register VLTCMP 0x1E4 R Bit 72 Reserved Bit 1 LVD16.1 Port Data Registers 16. General Purpose IO Ports16.1.1 P0 Data Table 16-1. P0 Data Register P0DATA0x00 R/W16.2.1 Int Enable 16.2 GPIO Port Configuration16.1.3 P2 Data Table 16-3. P2 Data Register P2DATA 0x02 R/W16.2.6 Pull Up Enable 16.2.7 Output EnableFigure 16-1. GPIO Block Diagram 16.2.9 P0.0/CLKIN Configuration16.2.10 P0.1/CLKOUT Configuration Table 16-7. P0.1/CLKOUT Configuration P01CR 0x06 R/W16.2.11 P0.2/INT0-P0.4/INT2 Configuration 16.2.13 P0.7 Configuration 16.2.12 P0.5/TIO0-P0.6/TIO1 ConfigurationTable 16-10. P0.7 Configuration P07CR 0x0C R/W 16.2.14 P1.0 ConfigurationTable 16-12. P1.1 Configuration P11CR 0x0E R/W 16.2.15 P1.1 Configuration16.2.16 P1.2 Configuration Table 16-13. P1.2 Configuration P12CR 0x0F R/WTable 16-15. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W 16.2.18 P1.4-P1.6 Configuration SCLK, SMOSI, SMISO16.2.19 P1.7 Configuration Table 16-16. P1.7 Configuration P17CR 0x14 R/WTable 16-18. P3 Configuration P3CR 0x16 R/W 16.2.21 P3 Configuration16.2.22 P4 Configuration Table 16-19. P4 Configuration P4CR 0x17 R/W17. Serial Peripheral Interface SPI Figure 17-1. SPI Block DiagramTable 17-2. SPI Configure Register SPICR 0x3D R/W 17.2 SPI Configure Register17.1 SPI Data Register Table 17-1. SPI Data Register SPIDATA 0x3C R/WDiagram Table 17-3. SPI Mode Timing vs. LSB First, CPOL, and CPHACPHA CPOL17.3 SPI Interface Pins 18. Timer RegistersFigure 18-1. 16-Bit Free Running Counter Block Diagram Table 18-1. Free Running Timer Low Order Byte FRTMRL 0x20 R/WFigure 18-2. Time Capture Block Diagram Table 18-2. Free Running Timer High Order Byte FRTMRH 0x21 R/WTable 18-3. Timer Configuration TMRCR 0x2A R/W 18.1.2 Time CaptureTable 18-5. Timer Capture 0 Rising TCAP0R 0x22 R/W Table 18-4. Capture Interrupt Enable TCAPINTE 0x2B R/WTable 18-6. Timer Capture 1 Rising TCAP1R 0x23 R/W Table 18-7. Timer Capture 0 Falling TCAP0F 0x24 R/W18.1.3 Programmable Interval Timer Table 18-8. Timer Capture 1 Falling TCAP1F 0x25 R/WTable 18-10. Programmable Interval Timer Low PITMRL 0x26 R Table 18-9. Capture Interrupt Status TCAPINTS 0x2C R/WTable 18-11. Programmable Interval Timer High PITMRH 0x27 R Table 18-12. Programmable Interval Reload Low PIRL 0x28 R/WTable 18-13. Programmable Interval Reload High PIRH 0x29 R/W Page 52 of Figure 18-3. Timer Functional Sequence DiagramFigure 18-5. Memory Mapped Registers Read and Write Timing Diagram Figure 18-4. 16-Bit Free Running Counter Loading Timing Diagram19. Interrupt Controller Figure 19-1. Interrupt Controller Block Diagram19.1 Architectural Description Table 19-1. Interrupt Priorities, Address, and Name19.3 Interrupt Latency 19.2 Interrupt Processing19.4 Interrupt Registers Table 19-2. Interrupt Clear 0 INTCLR0 0xDA R/WInterrupt Clear 2 INTCLR2 0xDC R/W Table 19-3. Interrupt Clear 1 INTCLR1 0xDB R/W19.4.2 Interrupt Mask Registers Table 19-5. Interrupt Mask 3 INTMSK3 0xDE R/WTable 19-6. Interrupt Mask 2 INTMSK2 0xDF R/W Table 19-7. Interrupt Mask 1 INTMSK1 0xE1 R/WPage 57 of Table 19-8. Interrupt Mask 0 INTMSK0 0xE0 R/W 19.4.3 Interrupt Vector Clear RegisterTable 19-9. Interrupt Vector Clear Register INTVC 0xE2 R/W 20. Absolute Maximum Ratings 20.1 DC CharacteristicsParameter ConditionsClock 20.2 AC CharacteristicsSPI Timing Figure 20-1. Clock TimingSCK CPOL=0 Figure 20-2. GPIO Timing DiagramSCK CPOL=1 MOSI MISOMISO MOSISS SCK CPOL=0 SCK CPOL=1 MOSI MISO MSB22. Package Handling 21. Ordering InformationSCK CPOL=0 SCK CPOL=1 MOSI MSBFigure 23-1. 24-Pin 300-Mil SOIC S13 23. Package DiagramsFigure 23-2. 24-Pin 300-Mil PDIP P13 3. DIMENSIONS IN INCHESFigure 23-3. 24-Pin QSOP O241 Figure 23-4. 28-Pin 5.3 mm Shrunk Small Outline Package O28Page 65 of Figure 23-5. 40-Pin 600-Mil Molded DIP P17 Figure 23-6. 48-Pin Shrunk Small Outline Package O48Page 66 of Document Number 24. Document History PageOrig. of SubmissionPSoC Solutions Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products
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