Cypress manual AC Test Loads and Waveforms, CYV15G0104TRB AC Electrical Characteristics

Page 18

CYV15G0104TRB

CYV15G0104TRB DC Electrical Characteristics (continued)

Parameter

Description

Test Conditions

Min.

Max.

Unit

VOLC

Output LOW Voltage

100differential load

VCC – 1.4

VCC – 0.7

V

 

(VCC Referenced)

VCC – 1.4

VCC – 0.7

V

 

 

150 differential load

VODIF

Output Differential Voltage

100differential load

450

900

mV

 

(OUT+) (OUT)

150differential load

560

1000

mV

 

 

Differential Serial Line Receiver Inputs: INA1±, INA2±

VDIFFs[9]

VIHE

VILE

IIHE

IILE

VICOM[11]

Input Differential Voltage (IN+) (IN)

 

100

1200

mV

Highest Input HIGH Voltage

 

 

VCC

V

Lowest Input LOW Voltage

 

VCC – 2.0

 

V

Input HIGH Current

VIN = VIHE Max.

 

1350

A

Input LOW Current

VIN = VILE Min.

–700

 

A

Common Mode input range

((VCC – 2.0V)+0.5)min,

+1.25

+3.1

V

 

(VCC – 0.5V) max.

 

 

 

Power Supply

 

 

Typ.

Max.

 

ICC [12, 13]

Max Power Supply Current

REFCLKB

Commercial

585

690

mA

 

 

= MAX

 

 

 

 

ICC [12, 13]

Typical Power Supply Current

REFCLKB

Commercial

560

660

mA

 

 

= 125 MHz

 

 

 

 

AC Test Loads and Waveforms

 

 

 

3.3V

 

 

 

 

 

 

 

 

 

R1 = 590

 

 

R1

 

 

 

RL = 100

 

RL

 

 

 

 

 

 

 

 

(Includes fixture and

 

 

 

 

R2 = 435

CL

 

 

 

 

 

 

 

 

 

CL

7 pF

 

R2

 

 

 

probe capacitance)

 

 

 

 

 

 

 

 

 

 

 

 

 

(Includes fixture and

 

 

 

 

(b) CML Output Test Load

[14]

 

 

 

 

 

 

 

probe capacitance)

 

 

 

 

 

 

 

 

(a) LVTTL Output Test Load[14]

 

 

 

 

 

 

 

 

 

 

3.0V

 

 

VIHE

 

VIHE

 

 

 

Vth = 1.4V

2.0V

 

2.0V

Vth = 1.4V

 

80%

80%

 

 

 

 

 

 

0.8V

 

0.8V

 

 

20%

 

 

20%

 

GND

 

 

VILE

 

 

 

 

 

 

 

 

 

 

VILE

 

 

 

1 ns

 

 

 

1 ns

270 ps

 

270 ps

 

 

 

 

 

 

 

 

(c) LVTTL Input Test Waveform[15]

 

 

(d) CML/LVPECL Input Test Waveform

 

CYV15G0104TRB AC Electrical Characteristics

 

 

 

 

 

 

 

 

Parameter

 

 

 

Description

 

 

 

 

Min.

 

Max

Unit

CYV15G0104TRB Transmitter LVTTL Switching Characteristics Over the Operating Range

 

 

 

 

fTS

TXCLKB Clock Cycle Frequency

 

 

 

 

19.5

 

150

MHz

tTXCLK

TXCLKB Period=1/fTS

 

 

 

 

 

6.66

 

51.28

ns

tTXCLKH[16]

TXCLKB HIGH Time

 

 

 

 

 

2.2

 

 

ns

tTXCLKL[16]

TXCLKB LOW Time

 

 

 

 

 

2.2

 

 

ns

Notes:

11.The common mode range defines the allowable range of INPUT+ and INPUTwhen INPUT+ = INPUT. This marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0.

12.Maximum ICC is measured with VCC = MAX,TA = 25°C, with all channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and outputs unloaded.

13.Typical ICC is measured under similar conditions except with VCC = 3.3V, TA = 25°C,with all channels enabled and one Serial Line Driver per channel sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded.

14.Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.

15.The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.

16.Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.

Document #: 38-02100 Rev. *B

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Contents Receive RX channel of the CYV15G0104TRB HOTLink FeaturesFunctional Description North First Street San Jose, CA Document # 38-02100 Rev. *BROUTA1 ± ROUTA2 ± TOUTB1 ± TOUTB2 ±Device Configuration and Control Block Diagram Reclocking Deserializer Path Block DiagramSerializer Path Block Diagram JtagPin Configuration Top View1 Pin Configuration Bottom View1 20 19 18 17 16Transmit Path Clock Signals Receive Path Data and Status SignalsName Characteristics Signal Description Receive Path Clock SignalsDevice Control Signals Signal Detect Amplitude Select Device Configuration and Control Bus SignalsInternal Device Configuration Latches Receive Channel Power ControlCYV15G0104TRB HOTLink II Operation CYV15G0104TRB Transmit Data PathCYV15G0104TRB Receive Data Path REFCLKB±Spdselb Txrateb Sdasela Signal Detect/Link FaultClock/Data Recovery TRGCLKA±Reclocker Serial Output Drivers Power ControlReclocker Output BusLatch Types Device Configuration and Control InterfaceDevice Reset State Static Latch ValuesReset sampled LOW disables all output drivers Disables all output driversTransmit Bist function is enabled Phase Alignment Buffer Document # 38-02100 Rev. *BJtag Support Jtag IDBISTSTA, RXDA0, RXDA1 Bistdatacompare 000 BisterrorBiststart BISTSTA, RXDA0, RXDA1 = Bistwait BistlastbadCYV15G0104TRB DC Electrical Characteristics Maximum RatingsOperating Range CYV15G0104TRB AC Electrical Characteristics AC Test Loads and WaveformsTxrateb = 1, Txckselb = Parameter Description Min Max UnitTxrateb = 0, Txckselb = TXRATEB= 0, Txckselb =PLL Characteristics CYV15G0104TRB Reclocker Output PLL CharacteristicsParameter Description Test Conditions Max Unit CYV15G0104TRB HOTLink II Transmitter Switching WaveformsCapacitance Transmit Interface Write Timing Txclkb selectedTxrate = Txrateb =Rxratea = Bus Configuration Write Timing No Connect VCC PowerReset Lvttl in PU GND GroundRXCLKA+ Lvttl OUT TXDB2 LvttlTXDB9 Lvttl Repdoa Lvttl OUTSpeed Ordering Code Package DiagramOrdering Information Package Type Operating Name RangeFRE REV ECN no Issue ORIG. Description of Change DateDocument History SUA