Cypress CYV15G0104TRB manual Pin Configuration Bottom View1, 20 19 18 17 16

Page 5

CYV15G0104TRB

Pin Configuration (Bottom View)[1]

20 19 18 17 16 15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

A

B

C

NC VCC

NC NC

TDO GND

NC VCC

NC NC

TRST LDTD EN

VCC

VCC

VCC

ROUT

A2–

ROUT

A2+

SPD

SELB

IN

GND

ROUT

IN

TOUT

GND

GND

TOUT

NC

VCC

NC

NC

NC

NC

A2–

A1–

A1–

B2–

B1–

IN

GND

ROUT

IN

TOUT

NC

GND

TOUT

VCC

VCC

NC

VCC

NC

VCC

A2+

A1+

A1+

B2+

B1+

NC

GND

DATA

DATA

DATA

DATA

GND

NC

NC

VCC

VCC

VCC

TMS

TDI

[0]

[2]

[4]

[6]

D

E

TMEN3 SCAN EN2

VCC VCC

VCC NC

VCC VCC

VCC

NC

GND GND GND DATA	DATA	DATA GND NC ULCA V	CC	INSELA	V	RESET	TCLK
[1]	[3]	[5]	CC		CC
[1]	[3]	[5]
				VCC	VCC	VCC	VCC

F

G

H

NC NC

NC SPD SELA

NC VCC

NC NC

NC	VCC	NC	NC
GND	GND	WREN	GND

GND GND

J

NC NC

K

NC NC

L

GND NC

M

GND NC

N

GND GND

P

GND GND

GND GND

NC NC

NC NC

NC NC

NC NC

GND GND

GND GND

GND	GND	GND	GND
GND	GND	GND	GND
GND	GND	NC	NC
GND	NC	NC	NC
NC	NC	NC	NC
GND	GND	GND	GND
NC	NC	NC	NC

R

T

U

VCC VCC

VCC VCC

RX BIST DA[0] STA

VCC VCC

VCC VCC

VCC RX

DA[4]

VCC

VCC

					NC	NC	NC	NC
					VCC	VCC	VCC	VCC
GND GND GND	REF	ADDR	GND GND NC	NC VCC	TX	TX	TX	TX
	CLKB–	[0]			DB[9]	DB[2]	DB[1]	DB[0]

V

RX RX

DA[1] DA[2]

RX RX

DA[5] DA[9]

VCC

VCC

GND GND	RE	REF	GND NC GND NC NC VCC NC	TX	TX	TX
	CLKOA	CLKB+		DB[8]	DB[4]	DB[3]

W	RX	TRG	LFIA
RX
DA[3]	DA[6]	CLKA+
Y	RX	TRG	TX
RX
DA[7]	DA[8]	CLKA–	ERRB

VCC

VCC

VCC

VCC

GND

GND

REPDO

RX

ADDR

ADDR

GND

NC

NC

V

NC

NC

TX

TX

A

CLKA+

[1]

[2]

CC

DB[7]

DB[5]

GND

GND

RX

GND

NC

TX

GND

NC

NC

VCC

NC

NC

TX

TX

CLKA–

CLKOB

CLKB

DB[6]

Document #: 38-02100 Rev. *B

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Contents Functional Description FeaturesReceive RX channel of the CYV15G0104TRB HOTLink North First Street San Jose, CA Document # 38-02100 Rev. *BTOUTB1 ± TOUTB2 ± ROUTA1 ± ROUTA2 ±Serializer Path Block Diagram Reclocking Deserializer Path Block DiagramDevice Configuration and Control Block Diagram JtagPin Configuration Top View1 20 19 18 17 16 Pin Configuration Bottom View1Receive Path Data and Status Signals Transmit Path Clock SignalsDevice Control Signals Name Characteristics Signal DescriptionReceive Path Clock Signals Internal Device Configuration Latches Device Configuration and Control Bus SignalsSignal Detect Amplitude Select Receive Channel Power ControlCYV15G0104TRB Transmit Data Path CYV15G0104TRB HOTLink II OperationSpdselb Txrateb CYV15G0104TRB Receive Data PathREFCLKB± Clock/Data Recovery Signal Detect/Link FaultSdasela TRGCLKA±Reclocker Power ControlReclocker Serial Output Drivers Output BusDevice Reset State Device Configuration and Control InterfaceLatch Types Static Latch ValuesTransmit Bist function is enabled Disables all output driversReset sampled LOW disables all output drivers Phase Alignment Buffer Document # 38-02100 Rev. *BBISTSTA, RXDA0, RXDA1 Jtag SupportJtag ID Biststart BISTSTA, RXDA0, RXDA1 = Bistwait BisterrorBistdatacompare 000 BistlastbadOperating Range CYV15G0104TRB DC Electrical CharacteristicsMaximum Ratings AC Test Loads and Waveforms CYV15G0104TRB AC Electrical CharacteristicsTxrateb = 0, Txckselb = Parameter Description Min Max UnitTxrateb = 1, Txckselb = TXRATEB= 0, Txckselb =CYV15G0104TRB Reclocker Output PLL Characteristics PLL CharacteristicsCapacitance CYV15G0104TRB HOTLink II Transmitter Switching WaveformsParameter Description Test Conditions Max Unit Transmit Interface Write Timing Txclkb selectedRxratea = Txrate =Txrateb = Bus Configuration Write Timing Reset Lvttl in PU VCC PowerNo Connect GND GroundTXDB9 Lvttl TXDB2 LvttlRXCLKA+ Lvttl OUT Repdoa Lvttl OUTOrdering Information Package DiagramSpeed Ordering Code Package Type Operating Name RangeDocument History REV ECN no Issue ORIG. Description of Change DateFRE SUA