Cypress CYV15G0104TRB manual Maximum Ratings, Operating Range

Page 17

Maximum Ratings

(Above which the useful life may be impaired. User guidelines only, not tested.)

Storage Temperature

–65°C to +150°C

Ambient Temperature with

 

Power Applied

–55°C to +125°C

Supply Voltage to Ground Potential

–0.5V to +3.8V

 

CYV15G0104TRB

Static Discharge Voltage

.......................................... > 2000 V

(per MIL-STD-883, Method 3015)

Latch-up Current

> 200 mA

Power-up Requirements

The CYV15G0104TRB requires one power supply. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.

DC Voltage Applied to LVTTL Outputs

Operating Range

 

 

 

 

in High-Z State .......................................–0.5V to VCC + 0.5V

Range

Ambient Temperature

VCC

Output Current into LVTTL Outputs (LOW)..................60 mA

Commercial

 

0°C to +70°C

+3.3V ±5%

DC Input Voltage....................................–0.5V to VCC + 0.5V

 

 

 

 

 

 

 

CYV15G0104TRB DC Electrical Characteristics

 

 

 

 

 

Parameter

Description

Test Conditions

 

Min.

Max.

 

Unit

LVTTL-compatible Outputs

 

 

 

 

 

 

VOHT

Output HIGH Voltage

IOH = 4 mA, VCC = Min.

2.4

 

 

V

VOLT

Output LOW Voltage

IOL = 4 mA, VCC = Min.

 

 

0.4

 

V

IOST

Output Short Circuit Current

VOUT = 0V[8], VCC = 3.3V

–20

–100

 

mA

IOZL

High-Z Output Leakage Current

VOUT = 0V, VCC

 

–20

20

 

µA

LVTTL-compatible Inputs

 

 

 

 

 

 

VIHT

Input HIGH Voltage

 

 

2.0

VCC + 0.3

 

V

VILT

Input LOW Voltage

 

 

–0.5

0.8

 

V

IIHT

Input HIGH Current

REFCLKB Input, VIN = VCC

 

1.5

 

mA

 

 

Other Inputs, VIN = VCC

 

 

+40

 

µA

IILT

Input LOW Current

REFCLKB Input, VIN = 0.0V

 

–1.5

 

mA

 

 

Other Inputs, VIN = 0.0V

 

 

–40

 

µA

IIHPDT

Input HIGH Current with internal pull-down

VIN = VCC

 

 

+200

 

µA

IILPUT

Input LOW Current with internal pull-up

VIN = 0.0V

 

 

–200

 

µA

LVDIFF Inputs: REFCLKB±

 

 

 

 

 

 

VDIFF[9]

Input Differential Voltage

 

 

400

VCC

 

mV

VIHHP

Highest Input HIGH Voltage

 

 

1.2

VCC

 

V

VILLP

Lowest Input LOW voltage

 

 

0.0

VCC/2

 

V

VCOMREF[10]

Common Mode Range

 

 

1.0

VCC – 1.2V

V

3-Level Inputs

 

 

 

 

 

 

VIHH

Three-Level Input HIGH Voltage

Min. VCC Max.

 

0.87 * VCC

VCC

 

V

VIMM

Three-Level Input MID Voltage

Min. VCC Max.

 

0.47 * VCC

0.53 * VCC

V

VILL

Three-Level Input LOW Voltage

Min. VCC Max.

 

0.0

0.13 * VCC

V

IIHH

Input HIGH Current

VIN = VCC

 

 

200

 

µA

IIMM

Input MID current

VIN = VCC/2

 

–50

50

 

µA

IILL

Input LOW current

VIN = GND

 

 

–200

 

µA

Differential CML Serial Outputs: OUTA1±, OUTA2±, OUTB1±, OUTB2±, OUTC1±, OUTC2±, OUTD1±, OUTD2±

 

 

VOHC

Output HIGH Voltage

100differential load

 

VCC – 0.5

VCC – 0.2

 

V

 

(VCC Referenced)

 

VCC – 0.5

VCC – 0.2

 

V

 

 

150 differential load

 

 

Notes:

8.Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.

9.This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when

the true (+) input is more positive than the complement () input. A logic-0 exists when the complement () input is more positive than true (+) input.

10.The common mode range defines the allowable range of REFCLKB+ and REFCLKBwhen REFCLKB+ = REFCLKB. This marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0.

Document #: 38-02100 Rev. *B

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Contents Functional Description FeaturesReceive RX channel of the CYV15G0104TRB HOTLink North First Street San Jose, CA Document # 38-02100 Rev. *BTOUTB1 ± TOUTB2 ± ROUTA1 ± ROUTA2 ±Serializer Path Block Diagram Reclocking Deserializer Path Block DiagramDevice Configuration and Control Block Diagram JtagPin Configuration Top View1 20 19 18 17 16 Pin Configuration Bottom View1Receive Path Data and Status Signals Transmit Path Clock SignalsDevice Control Signals Name Characteristics Signal DescriptionReceive Path Clock Signals Internal Device Configuration Latches Device Configuration and Control Bus SignalsSignal Detect Amplitude Select Receive Channel Power ControlCYV15G0104TRB Transmit Data Path CYV15G0104TRB HOTLink II OperationSpdselb Txrateb CYV15G0104TRB Receive Data PathREFCLKB± Clock/Data Recovery Signal Detect/Link FaultSdasela TRGCLKA±Reclocker Power ControlReclocker Serial Output Drivers Output BusDevice Reset State Device Configuration and Control InterfaceLatch Types Static Latch ValuesTransmit Bist function is enabled Disables all output driversReset sampled LOW disables all output drivers Phase Alignment Buffer Document # 38-02100 Rev. *BBISTSTA, RXDA0, RXDA1 Jtag SupportJtag ID Biststart BISTSTA, RXDA0, RXDA1 = Bistwait BisterrorBistdatacompare 000 BistlastbadOperating Range CYV15G0104TRB DC Electrical CharacteristicsMaximum Ratings AC Test Loads and Waveforms CYV15G0104TRB AC Electrical CharacteristicsTxrateb = 0, Txckselb = Parameter Description Min Max UnitTxrateb = 1, Txckselb = TXRATEB= 0, Txckselb =CYV15G0104TRB Reclocker Output PLL Characteristics PLL CharacteristicsCapacitance CYV15G0104TRB HOTLink II Transmitter Switching WaveformsParameter Description Test Conditions Max Unit Transmit Interface Write Timing Txclkb selectedRxratea = Txrate =Txrateb = Bus Configuration Write Timing Reset Lvttl in PU VCC PowerNo Connect GND GroundTXDB9 Lvttl TXDB2 LvttlRXCLKA+ Lvttl OUT Repdoa Lvttl OUTOrdering Information Package DiagramSpeed Ordering Code Package Type Operating Name RangeDocument History REV ECN no Issue ORIG. Description of Change DateFRE SUA