Cypress manual Capacitance, CYV15G0104TRB HOTLink II Transmitter Switching Waveforms

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CYV15G0104TRB

PLL Characteristics

Parameter	Description	Condition	Min. Typ. Max.	Unit
CYV15G0104TRB Receive PLL Characteristics Over the Operating Range
tRXLOCK	Receive PLL lock to input data stream (cold start)		376k	UI
	Receive PLL lock to input data stream		376k	UI
tRXUNLOCK	Receive PLL Unlock Rate		46	UI

Capacitance [16]

Parameter	Description	Test Conditions	Max.	Unit
CINTTL	TTL Input Capacitance	TA = 25°C, f0 = 1 MHz, VCC = 3.3V	7	pF
CINPECL	PECL input Capacitance	TA = 25°C, f0 = 1 MHz, VCC = 3.3V	4	pF

CYV15G0104TRB HOTLink II Transmitter Switching Waveforms

Transmit Interface

Write Timing

TXCLKB selected

TXCLKB

TXDB[9:0]

Transmit Interface

Write Timing

REFCLKB selected

TXRATEB = 0

REFCLKB

TXDB[9:0]

Transmit Interface

Write Timing

REFCLKB selected

TXRATEB = 1

REFCLKB

TXDB[9:0]

Note:

tTXCLK

tTXCLKH tTXCLKL

tTXDS tTXDH

tREFCLK

tREFH tREFL

tTREFDS tTREFDH

tREFCLK
tREFH	tREFL
Note 27
tTREFDS	tTREFDH tTREFDS	tTREFDH

27.When REFCLKB± is configured for half-rate operation (TXRATEB = 1) and data is captured using REFCLKB instead of a TXCLKB clock. Data is captured using both the rising and falling edges of REFCLKB.

Document #: 38-02100 Rev. *B

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Contents Functional Description FeaturesReceive RX channel of the CYV15G0104TRB HOTLink North First Street San Jose, CA Document # 38-02100 Rev. *BTOUTB1 ± TOUTB2 ± ROUTA1 ± ROUTA2 ±Serializer Path Block Diagram Reclocking Deserializer Path Block DiagramDevice Configuration and Control Block Diagram JtagPin Configuration Top View1 20 19 18 17 16 Pin Configuration Bottom View1Receive Path Data and Status Signals Transmit Path Clock SignalsName Characteristics Signal Description Receive Path Clock SignalsDevice Control Signals Internal Device Configuration Latches Device Configuration and Control Bus SignalsSignal Detect Amplitude Select Receive Channel Power ControlCYV15G0104TRB Transmit Data Path CYV15G0104TRB HOTLink II OperationCYV15G0104TRB Receive Data Path REFCLKB±Spdselb Txrateb Clock/Data Recovery Signal Detect/Link FaultSdasela TRGCLKA±Reclocker Power ControlReclocker Serial Output Drivers Output BusDevice Reset State Device Configuration and Control InterfaceLatch Types Static Latch ValuesTransmit Bist function is enabled Disables all output driversReset sampled LOW disables all output drivers Phase Alignment Buffer Document # 38-02100 Rev. *BJtag Support Jtag IDBISTSTA, RXDA0, RXDA1 Biststart BISTSTA, RXDA0, RXDA1 = Bistwait BisterrorBistdatacompare 000 BistlastbadCYV15G0104TRB DC Electrical Characteristics Maximum RatingsOperating Range AC Test Loads and Waveforms CYV15G0104TRB AC Electrical CharacteristicsTxrateb = 0, Txckselb = Parameter Description Min Max UnitTxrateb = 1, Txckselb = TXRATEB= 0, Txckselb =CYV15G0104TRB Reclocker Output PLL Characteristics PLL CharacteristicsCapacitance CYV15G0104TRB HOTLink II Transmitter Switching WaveformsParameter Description Test Conditions Max Unit Transmit Interface Write Timing Txclkb selectedTxrate = Txrateb =Rxratea = Bus Configuration Write Timing Reset Lvttl in PU VCC PowerNo Connect GND GroundTXDB9 Lvttl TXDB2 LvttlRXCLKA+ Lvttl OUT Repdoa Lvttl OUTOrdering Information Package DiagramSpeed Ordering Code Package Type Operating Name RangeDocument History REV ECN no Issue ORIG. Description of Change DateFRE SUA