Cypress CYV15G0104TRB manual Transmit Path Clock Signals, Receive Path Data and Status Signals

CYV15G0104TRB

Pin Definitions

CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer

Name	I/O Characteristics	Signal Description
Transmit Path Data and Status Signals
TXDB[9:0]	LVTTL Input,	Transmit Data Inputs. TXDB[9:0] data inputs are captured on the rising edge of the
	synchronous,	transmit interface clock. The transmit interface clock is selected by the TXCKSELB latch
	sampled by	via the device configuration interface.
	TXCLKB↑ or
	REFCLKB↑[2]
TXERRB	LVTTL Output,	Transmit Path Error. TXERRB is asserted HIGH to indicate detection of a transmit
	synchronous to	Phase-Align Buffer underflow or overflow. If an underflow or overflow condition is
	REFCLKB↑ [3],	detected, TXERRB, is asserted HIGH and remains asserted until the transmit Phase-Align
	asynchronous to	Buffer is re-centered with the PABRSTB latch via the device configuration interface. When
	transmit channel	TXBISTB = 0, the BIST progress is presented on the TXERRB output. The TXERRB
	enable / disable,	signal pulses HIGH for one transmit-character clock period to indicate a pass through the
	asynchronous to loss	BIST sequence once every 511 character times.
	or return of	TXERRB is also asserted HIGH, when any of the following conditions is true:
	REFCLKB±
		• The TXPLL is powered down. This occurs when TOE2B and TOE1B are both disabled

by setting TOE2B = 0 and TOE1B = 0.

• The absence of the REFCLKB± signal.

Transmit Path Clock Signals

REFCLKB±	Differential LVPECL
	or single-ended
	LVTTL input clock
TXCLKB	LVTTL Clock Input,
	internal pull-down

TXCLKOB LVTTL Output

Reference Clock. REFCLKB± clock inputs are used as the timing reference for the transmit PLL. This input clock may also be selected to clock the transmit parallel interface. When driven by a single-ended LVCMOS or LVTTL clock source, connect the clock source to either the true or complement REFCLKB input, and leave the alternate REFCLKB input open (floating). When driven by an LVPECL clock source, the clock must be a differential clock, using both inputs.

Transmit Path Input Clock. When configuration latch TXCKSELB = 0, the associated TXCLKB input is selected as the character-rate input clock for the TXDB[9:0] input. In this mode, the TXCLKB input must be frequency-coherent to its TXCLKOB output clock, but may be offset in phase by any amount. Once initialized, TXCLKB is allowed to drift in phase by as much as ±180 degrees. If the input phase of TXCLKB drifts beyond the handling capacity of the Phase Align Buffer, TXERRB is asserted to indicate the loss of data, and remains asserted until the Phase Align Buffer is initialized. The phase of TXCLKB relative to REFCLKB± is initialized when the configuration latch PABRSTB is written as 0. When TXERRB is deasserted, the Phase Align Buffer is initialized and input characters are correctly captured.

Transmit Clock Output. TXCLKOB output clock is synthesized by the transmit PLL and operates synchronous to the internal transmit character clock. TXCLKOB operates at either the same frequency as REFCLKB± (TXRATEB = 0), or at twice the frequency of REFCLKB± (TXRATEB = 1). The transmit clock outputs have no fixed phase relationship to REFCLKB±.

Receive Path Data and Status Signals

RXDA[9:0]	LVTTL Output,	Parallel Data Output. RXDA[9:0] parallel data outputs change relative to the receive
	synchronous to the	interface clock. If RXCLKA± is a full-rate clock, the RXCLKA± clock outputs are comple-
	RXCLKA ± output	mentary clocks operating at the character rate. The RXDA[9:0] outputs for the associated
		receive channels follow rising edge of RXCLKA+ or falling edge of RXCLKA–. If RXCLKA±
		is a half-rate clock, the RXCLKA± clock outputs are complementary clocks operating at
		half the character rate. The RXDA[9:0] outputs for the associated receive channels follow
		both the falling and rising edges of the associated RXCLKA± clock outputs.
		When BIST is enabled on the receive channel, the BIST status is presented on the
		RXDA[1:0] and BISTSTA outputs. See Table 6 for each status reported by the BIST state
		machine. Also, while BIST is enabled, the RXDA[9:2] outputs should be ignored.

Notes:

2.When REFCLKB± is configured for half-rate operation, these inputs are sampled relative to both the rising and falling edges of the associated REFCLKB±.

3.When REFCLKB± is configured for half-rate operation, this output is presented relative to both the rising and falling edges of the associated REFCLKB±.

Document #: 38-02100 Rev. *B Page 6 of 27

[+] Feedback