Cypress CYV15G0104TRB manual Pin Configuration Top View1

Page 4

CYV15G0104TRB

Pin Configuration (Top View)[1]

1	2	3	4	5
A				VCC
NC	NC	NC	NC
B		VCC		VCC
VCC	NC		NC
C		VCC	VCC	VCC
TDI	TMS
D		VCC		VCC
TCLK	RESET		INSELA
E	VCC	VCC	VCC
VCC
F		VCC
NC	NC		NC
G	WREN	GND	GND
GND
H	GND	GND	GND
GND
J	GND	GND	GND
GND
K	NC	GND	GND
NC
L	NC	NC	GND
NC
M	NC	NC	NC
NC
N	GND	GND	GND
GND
P	NC	NC	NC
NC
R

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

NC

TOUT

GND

GND

TOUT

IN

ROUT

GND

IN

ROUT

VCC

VCC

NC

VCC

NC

B1–

B2–

A1–

A1–

A2–

A2–

VCC

TOUT

GND

NC

TOUT

IN

ROUT

GND

IN

ROUT

VCC

NC

NC

NC

NC

B1+

B2+

A1+

A1+

A2+

A2+

NC

NC

GND

DATA

DATA

DATA

DATA

GND

NC

SPD

VCC

LDTD

TRST

GND

TDO

[6]

[4]

[2]

[0]

SELB

EN

ULCA

NC

GND

DATA

DATA

DATA

GND

GND

GND

NC

VCC

NC

VCC

SCAN

TMEN3

[5]

[3]

[1]

EN2

VCC

VCC

VCC

VCC

VCC

NC

NC

NC

NC

NC

SPD

NC

SELA

GND

GND

GND

GND

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

GND

NC

NC

NC

GND

GND

GND

GND

GND

GND

GND

GND

GND

NC	NC	NC	NC
T
VCC	VCC	VCC	VCC
U
TX	TX	TX	TX	VCC
DB[0]	DB[1]	DB[2]	DB[9]
V				VCC
TX	TX	TX	NC	VCC
DB[3]	DB[4]	DB[8]
W				VCC
TX	TX	NC	NC	VCC
DB[5]	DB[7]
Y				VCC
TX	TX	NC	NC	VCC
DB[6]	CLKB

Note:

1.NC = Do not connect.

NC	NC	GND	GND	ADDR	REF	GND	GND	GND	VCC
				[0]	CLKB–
NC	NC	GND	NC	GND	REF	RE	GND	GND	VCC
					CLKB+	CLKOA
NC	NC	GND	ADDR	ADDR	RX	REPDO	GND	GND	V
			[2]	[1]	CLKA+	A			CC
			[2]	[1]	CLKA+	A
NC	NC	GND	TX	NC	GND	RX	GND	GND	VCC
			CLKOB			CLKA–

	VCC	VCC	VCC	VCC
	VCC	VCC	VCC	VCC
VCC	RX	VCC	BIST	RX
	DA[4]		STA	DA[0]
VCC	RX	RX	RX	RX
	DA[9]	DA[5]	DA[2]	DA[1]
VCC	LFIA	TRG	RX	RX
		CLKA+	DA[6]	DA[3]
VCC	TX	TRG	RX	RX
	ERRB	CLKA–	DA[8]	DA[7]

Document #: 38-02100 Rev. *B

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Contents Features Functional DescriptionReceive RX channel of the CYV15G0104TRB HOTLink North First Street San Jose, CA Document # 38-02100 Rev. *BROUTA1 ± ROUTA2 ± TOUTB1 ± TOUTB2 ±Reclocking Deserializer Path Block Diagram Serializer Path Block DiagramDevice Configuration and Control Block Diagram JtagPin Configuration Top View1 Pin Configuration Bottom View1 20 19 18 17 16Transmit Path Clock Signals Receive Path Data and Status SignalsReceive Path Clock Signals Name Characteristics Signal DescriptionDevice Control Signals Device Configuration and Control Bus Signals Internal Device Configuration LatchesSignal Detect Amplitude Select Receive Channel Power ControlCYV15G0104TRB HOTLink II Operation CYV15G0104TRB Transmit Data PathREFCLKB± CYV15G0104TRB Receive Data PathSpdselb Txrateb Signal Detect/Link Fault Clock/Data RecoverySdasela TRGCLKA±Power Control ReclockerReclocker Serial Output Drivers Output BusDevice Configuration and Control Interface Device Reset StateLatch Types Static Latch ValuesDisables all output drivers Transmit Bist function is enabledReset sampled LOW disables all output drivers Phase Alignment Buffer Document # 38-02100 Rev. *BJtag ID Jtag SupportBISTSTA, RXDA0, RXDA1 Bisterror Biststart BISTSTA, RXDA0, RXDA1 = BistwaitBistdatacompare 000 BistlastbadMaximum Ratings CYV15G0104TRB DC Electrical CharacteristicsOperating Range CYV15G0104TRB AC Electrical Characteristics AC Test Loads and WaveformsParameter Description Min Max Unit Txrateb = 0, Txckselb =Txrateb = 1, Txckselb = TXRATEB= 0, Txckselb =PLL Characteristics CYV15G0104TRB Reclocker Output PLL CharacteristicsCYV15G0104TRB HOTLink II Transmitter Switching Waveforms CapacitanceParameter Description Test Conditions Max Unit Transmit Interface Write Timing Txclkb selectedTxrateb = Txrate =Rxratea = Bus Configuration Write Timing VCC Power Reset Lvttl in PUNo Connect GND GroundTXDB2 Lvttl TXDB9 LvttlRXCLKA+ Lvttl OUT Repdoa Lvttl OUTPackage Diagram Ordering InformationSpeed Ordering Code Package Type Operating Name RangeREV ECN no Issue ORIG. Description of Change Date Document HistoryFRE SUA