Cypress CYV15G0104TRB manual Name Characteristics Signal Description, Receive Path Clock Signals

CYV15G0104TRB

Pin Definitions (continued)

CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer

Name	I/O Characteristics	Signal Description
BISTSTA	LVTTL Output,	BIST Status Output. When RXBISTA[1:0] = 10, BISTSTA (along with RXDA[1:0])
	synchronous to the	displays the status of the BIST reception. See Table 6 for the BIST status reported for
	RXCLKA ± output	each combination of BISTSTA and RXDA[1:0].
		When RXBISTA[1:0] ≠ 10, BISTSTA should be ignored.
REPDOA	Asynchronous to	Reclocker Powered Down Status Output. REPDOA is asserted HIGH, when the
	reclocker output	reclocker output logic is powered down. This occurs when ROE2A and ROE1A are both
	channel	disabled by setting ROE2A = 0 and ROE1A = 0.
	enable/disable

Receive Path Clock Signals

TRGCLKA± Differential LVPECL or single-ended LVTTL input clock

RXCLKA± LVTTL Output Clock

RECLKOA LVTTL Output

Device Control Signals

RESET	LVTTL Input,
	asynchronous,
	internal pull-up
LDTDEN	LVTTL Input,
	internal pull-up

ULCA	LVTTL Input,
	internal pull-up

CDR PLL Training Clock. TRGCLKA± clock inputs are used as the reference source for the frequency detector (Range Controller) of the receive PLL to reduce PLL acquisition time.

In the presence of valid serial data, the recovered clock output of the receive CDR PLL (RXCLKA±) has no frequency or phase relationship with TRGCLKA±.

When driven by a single-ended LVCMOS or LVTTL clock source, connect the clock source to either the true or complement TRGCLKA input, and leave the alternate TRGCLKA input open (floating). When driven by an LVPECL clock source, the clock must be a differential clock, using both inputs.

Receive Clock Output. RXCLKA± is the receive interface clock used to control timing of the RXDA[9:0] parallel outputs. These true and complement clocks are used to control timing of data output transfers. These clocks are output continuously at either the half- character rate (1/20th the serial bit-rate) or character rate (1/10th the serial bit-rate) of the data being received, as selected by RXRATEA.

Reclocker Clock Output. RECLKOA output clock is synthesized by the reclocker output PLL and operates synchronous to the internal recovered character clock. RECLKOA operates at either the same frequency as RXCLKA± (RXRATEA = 0), or at twice the frequency of RXCLKA± (RXRATEA = 1).The reclocker clock outputs have no fixed phase relationship to RXCLKA±.

Asynchronous Device Reset. RESET initializes all state machines, counters, and configuration latches in the device to a known state. RESET must be asserted LOW for a minimum pulse width. When the reset is removed, all state machines, counters and config- uration latches are at an initial state. See Table 4 for the initialize values of the device configuration latches.

Level Detect Transition Density Enable. When LDTDEN is HIGH, the Signal Level Detector, Range Controller, and Transition Density Detector are all enabled to determine if the RXPLL tracks TRGCLKA± or the selected input serial data stream. If the Signal Level Detector, Range Controller, or Transition Density Detector are out of their respective limits while LDTDEN is HIGH, the RXPLL locks to TRGCLKA± until such a time they become valid. SDASEL[2..1]A[1:0] is used to configure the trip level of the Signal Level Detector. The Transition Density Detector limit is one transition in every 60 consecutive bits. When LDTDEN is LOW, only the Range Controller is used to determine if the RXPLL tracks TRGCLKA± or the selected input serial data stream. it is recommended to set LDTDEN = HIGH.

Use Local Clock. When ULCA is LOW, the RXPLL is forced to lock to TRGCLKA± instead of the received serial data stream. While ULCA is LOW, the link fault indicator LFIA is LOW indicating a link fault.

When ULCA is HIGH, the RXPLL performs Clock and Data Recovery functions on the input data streams. This function is used in applications in which a stable RXCLKA± is needed. In cases when there is an absence of valid data transitions for a long period of time, or the high-gain differential serial inputs (INA±) are left floating, there may be brief frequency excursions of the RXCLKA± outputs from TRGCLKA±.

Document #: 38-02100 Rev. *B Page 7 of 27

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