Cypress CYV15G0104TRB manual Txrate =, Txrateb =, Rxratea =

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CYV15G0104TRB

CYV15G0104TRB HOTLink II Transmitter Switching Waveforms (continued)

Transmit Interface	tREFCLK
TXCLKOB Timing	tREFCLK
tREFH	tREFL
TXRATE = 1

REFCLKB

Note 28

tTXCLKO

Note 29

TXCLKOB (internal)

Transmit Interface
TXCLKOB Timing	tREFCLK
tREFH	tREFL
TXRATEB = 0	Note28
REFCLKB

Note29

TXCLKOB

tTXCLKO

Switching Waveforms for the CYV15G0104TRB HOTLink II Receiver

Receive Interface

Read TimingtRXCLKP

RXRATEA = 0

RXCLKA+

RXCLKA–

tRXDV–

RXDA[9:0]

tRXDV+

Notes:

28.The TXCLKOB output remains at the character rate regardless of the state of TXRATEB and does not follow the duty cycle of REFCLKB±.

29.The rising edge of TXCLKOB output has no direct phase relationship to the REFCLKB± input.

Document #: 38-02100 Rev. *B

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Contents Receive RX channel of the CYV15G0104TRB HOTLink FeaturesFunctional Description North First Street San Jose, CA Document # 38-02100 Rev. *BROUTA1 ± ROUTA2 ± TOUTB1 ± TOUTB2 ±Device Configuration and Control Block Diagram Reclocking Deserializer Path Block DiagramSerializer Path Block Diagram JtagPin Configuration Top View1 Pin Configuration Bottom View1 20 19 18 17 16Transmit Path Clock Signals Receive Path Data and Status SignalsReceive Path Clock Signals Name Characteristics Signal DescriptionDevice Control Signals Signal Detect Amplitude Select Device Configuration and Control Bus SignalsInternal Device Configuration Latches Receive Channel Power ControlCYV15G0104TRB HOTLink II Operation CYV15G0104TRB Transmit Data PathREFCLKB± CYV15G0104TRB Receive Data PathSpdselb Txrateb Sdasela Signal Detect/Link FaultClock/Data Recovery TRGCLKA±Reclocker Serial Output Drivers Power ControlReclocker Output BusLatch Types Device Configuration and Control InterfaceDevice Reset State Static Latch ValuesReset sampled LOW disables all output drivers Disables all output driversTransmit Bist function is enabled Phase Alignment Buffer Document # 38-02100 Rev. *BJtag ID Jtag SupportBISTSTA, RXDA0, RXDA1 Bistdatacompare 000 BisterrorBiststart BISTSTA, RXDA0, RXDA1 = Bistwait BistlastbadMaximum Ratings CYV15G0104TRB DC Electrical CharacteristicsOperating Range CYV15G0104TRB AC Electrical Characteristics AC Test Loads and WaveformsTxrateb = 1, Txckselb = Parameter Description Min Max UnitTxrateb = 0, Txckselb = TXRATEB= 0, Txckselb =PLL Characteristics CYV15G0104TRB Reclocker Output PLL CharacteristicsParameter Description Test Conditions Max Unit CYV15G0104TRB HOTLink II Transmitter Switching WaveformsCapacitance Transmit Interface Write Timing Txclkb selectedTxrateb = Txrate =Rxratea = Bus Configuration Write Timing No Connect VCC PowerReset Lvttl in PU GND GroundRXCLKA+ Lvttl OUT TXDB2 LvttlTXDB9 Lvttl Repdoa Lvttl OUTSpeed Ordering Code Package DiagramOrdering Information Package Type Operating Name RangeFRE REV ECN no Issue ORIG. Description of Change DateDocument History SUA