Cypress CY7C1314AV18, CY7C1312AV18 manual Switching Characteristics Over the Operating Range 16,17

CY7C1310AV18

PRELIMINARY

CY7C1312AV18

CY7C1314AV18

Switching Characteristics Over the Operating Range[16,17]

Cypress

Consortium

167 MHz

133 MHz

Parameter

Parameter

Description

Min.

Max.

Min.

Max.

Unit

tCYC

tKHKH

K Clock and C Clock Cycle Time

6.0

7.9

7.5

8.4

ns

tKH

tKHKL

Input Clock (K/K

and C/C) HIGH

2.4

–

3.0

–

ns

tKL

tKLKH

Input Clock (K/K

and C/C) LOW

2.4

–

3.0

–

ns

tKHKH

tKHKH

K/K

Clock Rise to

K/K Clock Rise and C/C to C/C Rise (rising

2.7

–

3.38

–

ns

edge to rising edge)

tKHCH

tKHCH

K/K

Clock Rise to C/C

Clock Rise (rising edge to rising edge)

0.0

2.8

0.0

3.55

ns

Set-up Times

tSA

tSA

Address Set-up to K Clock Rise

0.5

–

0.5

–

ns

tSC

tSC

Control Set-up to Clock (K,

K) Rise (RPS, WPS)

0.5

–

0.5

–

ns

tSCDDR

tSC

Double Data Rate Control Set-up to Clock (K,

K) Rise

0.5

–

0.5

–

ns

(BWS0, BWS1, BWS3, BWS4)

tSD

tSD

D[X:0] Set-up to Clock (K and

K) Rise

0.5

–

0.5

–

ns

Hold Times

tHA

tHA

Address Hold after Clock (K and

K) Rise

0.5

–

0.5

–

ns

tHC

tHC

Control Hold after Clock (K and

K) Rise (RPS, WPS)

0.5

–

0.5

–

ns

tHCDDR

tHC

Double Data Rate Control Hold after Clock (K and

K) Rise

0.5

–

0.5

–

ns

(BWS0, BWS1 , BWS3, BWS4)

tHD

tHD

D[X:0] Hold after Clock (K and

K) Rise

0.5

–

0.5

–

ns

Output Times

tCO

tCHQV

C/C

Clock Rise (or K/K

in Single Clock Mode) to Data Valid

–

0.50

–

0.50

ns

tDOH

tCHQX

Data Output Hold after Output C/C

Clock Rise (Active to

–0.50

–

–0.50

–

ns

Active)

tCCQO

tCHCQV

C/C

Clock Rise to Echo Clock Valid

–

0.50

–

0.50

ns

tCQOH

tCHCQX

Echo Clock Hold after C/C

Clock Rise

–0.50

–

–0.50

–

ns

tCQD

tCQHQV

Echo Clock High to Data Valid

–

0.40

–

0.40

ns

tCQDOH

tCQHQX

Echo Clock High to Data Invalid

–0.40

–

–0.40

–

ns

tCHZ

tCHZ

Clock (C and

C) Rise to High-Z (Active to High-Z)[18,19]

–

0.50

–

0.50

ns

t

t

CLZ

Clock (C and

C) Rise to Low-Z[18,19]

–0.50

–

–0.50

–

ns

CLZ

DLL Timing

tKC Var

tKC Var

Clock Phase Jitter

–

0.20

–

0.20

ns

tKC lock

tKC lock

DLL Lock Time (K, C)

1024

–

1024

-

cycl

es

tKC Reset

tKC Reset

K Static to DLL Reset

30

30

ns

Thermal Resistance[20]

Parameter	Description	Test Conditions	165 FBGAPackage	Unit
ΘJA	Thermal Resistance	Test conditions follow standard test methods and	16.7	°C/W
	(Junction to Ambient)	procedures for measuring thermal impedence, per
		EIA / JESD51.
ΘJC	Thermal Resistance		2.5	°C/W
	(Junction to Case)

Notes:

16.All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequncy, it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.

17.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC test loads.

18.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

19.At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.

Document #: 38-05497 Rev. *A Page 10 of 21

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