Cypress CY7C1310AV18, CY7C1312AV18 manual Write Cycle Descriptions CY7C1314AV18 2, Bws, Comments

Page 8

 

CY7C1310AV18

PRELIMINARY

CY7C1312AV18

CY7C1314AV18

 

 

Write Cycle Descriptions (CY7C1310AV18 and CY7C1312AV18) [2, 8]

BWS0

BWS1

K

K

Comments

L

L

L-H

During the Data portion of a Write sequence :

 

 

 

 

CY7C1310AV18 both nibbles (D[7:0]) are written into the device,

 

 

 

 

CY7C1312AV18 both bytes (D[17:0]) are written into the device.

L

L

L-H

During the Data portion of a Write sequence :

 

 

 

 

CY7C1310AV18 both nibbles (D[7:0]) are written into the device,

 

 

 

 

CY7C1312AV18 both bytes (D[17:0]) are written into the device.

L

H

L-H

During the Data portion of a Write sequence :

 

 

 

 

CY7C1310AV18 only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered,

 

 

 

 

CY7C1312AV18 only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered.

L

H

L-H

During the Data portion of a Write sequence :

 

 

 

 

CY7C1310AV18 only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered,

 

 

 

 

CY7C1312AV18 only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered.

H

L

L-H

During the Data portion of a Write sequence :

 

 

 

 

CY7C1310AV18 only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered,

 

 

 

 

CY7C1312AV18 only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered.

H

L

L-H

During the Data portion of a Write sequence :

 

 

 

 

CY7C1310AV18 only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered,

 

 

 

 

CY7C1312AV18 only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered.

H

H

L-H

No data is written into the devices during this portion of a write operation.

 

 

 

 

 

H

H

L-H

No data is written into the devices during this portion of a write operation.

 

 

 

 

 

Write Cycle Descriptions (CY7C1314AV18) [2, 8]

BWS0

BWS1

BWS2

BWS3

K

K

Comments

L

L

L

L

L-H

-

During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into

 

 

 

 

 

 

the device.

L

L

L

L

-

L-H

During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into

 

 

 

 

 

 

the device.

L

H

H

H

L-H

-

During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written

 

 

 

 

 

 

into the device. D[35:9] will remain unaltered.

L

H

H

H

-

L-H

During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written

 

 

 

 

 

 

into the device. D[35:9] will remain unaltered.

H

L

H

H

L-H

-

During the Data portion of a Write sequence, only the byte (D[17:9]) is written into

 

 

 

 

 

 

the device. D[8:0] and D[35:18] will remain unaltered.

H

L

H

H

-

L-H

During the Data portion of a Write sequence, only the byte (D[17:9]) is written into

 

 

 

 

 

 

the device. D[8:0] and D[35:18] will remain unaltered.

H

H

L

H

L-H

-

During the Data portion of a Write sequence, only the byte (D[26:18]) is written into

 

 

 

 

 

 

the device. D[17:0] and D[35:27] will remain unaltered.

H

H

L

H

-

L-H

During the Data portion of a Write sequence, only the byte (D[26:18]) is written into

 

 

 

 

 

 

the device. D[17:0] and D[35:27] will remain unaltered.

H

H

H

L

L-H

 

During the Data portion of a Write sequence, only the byte (D[35:27]) is written into

 

 

 

 

 

 

the device. D[26:0] will remain unaltered.

H

H

H

L

-

L-H

During the Data portion of a Write sequence, only the byte (D[35:27]) is written into

 

 

 

 

 

 

the device. D[26:0] will remain unaltered.

H

H

H

H

L-H

-

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

H

H

H

H

-

L-H

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

Document #: 38-05497 Rev. *A

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Contents Features ConfigurationsLogic Block Diagram CY7C1310AV18 Functional DescriptionLogic Block Diagram CY7C1312AV18 Logic Block Diagram CY7C1314AV18Selection Guide 167 MHz 133 MHz UnitTMS TDI Pin ConfigurationsVSS Pin Definitions Pin Name Pin DescriptionOperations WPSNegative Output Clock Input Negative Input Clock InputIs referenced with respect to TDO for JtagIntroduction RPS WPS Application Example1DLL Comments Write Cycle Descriptions CY7C1314AV18 2BWS DC Electrical Characteristics Over the Operating Range9,14 AC Electrical Characteristics Over the Operating RangeMaximum Ratings Operating RangeSwitching Characteristics Over the Operating Range 16,17 Thermal Resistance20Capacitance20 AC Test Loads and WaveformsParameter Description Test Conditions Max Unit Input Capacitance TA = 25C, f = 1 MHz VDD =Preliminary Read/Write/Deselect SequenceIeee 1149.1 Serial Boundary Scan Jtag IdcodeSample Z SAMPLE/PRELOADBypass ExtestTAP Controller State Diagram24 EXIT2-IR UPDATE-DR UPDATE-IRTAP Controller Block Diagram Parameter Description Test Conditions Min Max UnitParameter Description Min Max Unit TAP AC Switching Characteristics Over the Operating Range26TAP Timing and Test Conditions27 Identification Register Definitions Scan Register SizesInstruction Codes Boundary Scan Order10F Package Diagram Ordering InformationDocument History REVDIM VBL