Cypress CY7C1310AV18 manual Sample Z, Sample/Preload, Bypass, Extest Output BUS TRI-STATE

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CY7C1310AV18

CY7C1312AV18

PRELIMINARYCY7C1314AV18

is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state.

SAMPLE/PRELOAD

SAMPLE / PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE / PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Cap- ture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possi- ble that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE / PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the bound- ary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells pri- or to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required - that is, while data captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

EXTEST

The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state.

EXTEST OUTPUT BUS TRI-STATE

IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #47. When this scan cell, called the "extest output bus tristate", is latched into the preload register during the "Update-DR" state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the "Shift-DR" state. During "Update-DR", the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the "Test-Logic-Reset" state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

Document #: 38-05497 Rev. *A

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Contents Logic Block Diagram CY7C1310AV18 FeaturesConfigurations Functional DescriptionSelection Guide Logic Block Diagram CY7C1312AV18Logic Block Diagram CY7C1314AV18 167 MHz 133 MHz UnitTMS TDI Pin ConfigurationsVSS Operations Pin DefinitionsPin Name Pin Description WPSIs referenced with respect to Negative Output Clock InputNegative Input Clock Input TDO for JtagIntroduction RPS WPS Application Example1DLL Comments Write Cycle Descriptions CY7C1314AV18 2BWS Maximum Ratings DC Electrical Characteristics Over the Operating Range9,14AC Electrical Characteristics Over the Operating Range Operating RangeSwitching Characteristics Over the Operating Range 16,17 Thermal Resistance20Parameter Description Test Conditions Max Unit Capacitance20AC Test Loads and Waveforms Input Capacitance TA = 25C, f = 1 MHz VDD =Preliminary Read/Write/Deselect SequenceIeee 1149.1 Serial Boundary Scan Jtag IdcodeBypass Sample ZSAMPLE/PRELOAD ExtestTAP Controller State Diagram24 EXIT2-IR UPDATE-DR UPDATE-IRTAP Controller Block Diagram Parameter Description Test Conditions Min Max UnitParameter Description Min Max Unit TAP AC Switching Characteristics Over the Operating Range26TAP Timing and Test Conditions27 Instruction Codes Identification Register DefinitionsScan Register Sizes Boundary Scan Order10F Package Diagram Ordering InformationDIM Document HistoryREV VBL
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