Cypress CY7C1312AV18, CY7C1314AV18, CY7C1310AV18 manual Document History, Rev, Dim, Vbl

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CY7C1310AV18

CY7C1312AV18

PRELIMINARYCY7C1314AV18

Document History Page

Document Title: CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 18-Mb QDR™-II SRAM 2-Word Burst Architecture

Document Number: 38-05497

REV.	ECN No.	Issue Date	Orig. of	Description of Change
REV.	ECN No.	Issue Date	Change	Description of Change

**	208405	see ECN	DIM	New Data Sheet

*A	230396	see ECN	VBL	Upload datasheet to the internet

Document #: 38-05497 Rev. *A

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Contents Configurations FeaturesLogic Block Diagram CY7C1310AV18 Functional DescriptionLogic Block Diagram CY7C1314AV18 Logic Block Diagram CY7C1312AV18Selection Guide 167 MHz 133 MHz UnitPin Configurations VSSTMS TDI Pin Name Pin Description Pin DefinitionsOperations WPSNegative Input Clock Input Negative Output Clock InputIs referenced with respect to TDO for JtagIntroduction Application Example1 DLLRPS WPS Write Cycle Descriptions CY7C1314AV18 2 BWSComments AC Electrical Characteristics Over the Operating Range DC Electrical Characteristics Over the Operating Range9,14Maximum Ratings Operating RangeThermal Resistance20 Switching Characteristics Over the Operating Range 16,17AC Test Loads and Waveforms Capacitance20Parameter Description Test Conditions Max Unit Input Capacitance TA = 25C, f = 1 MHz VDD =Read/Write/Deselect Sequence PreliminaryIdcode Ieee 1149.1 Serial Boundary Scan JtagSAMPLE/PRELOAD Sample ZBypass ExtestEXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram24Parameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP AC Switching Characteristics Over the Operating Range26 TAP Timing and Test Conditions27Parameter Description Min Max Unit Scan Register Sizes Identification Register DefinitionsInstruction Codes Boundary Scan Order10F Ordering Information Package DiagramREV Document HistoryDIM VBL