Cypress CY7C1310AV18, CY7C1312AV18, CY7C1314AV18 manual Capacitance20, AC Test Loads and Waveforms

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CY7C1310AV18

 

 

 

PRELIMINARY

CY7C1312AV18

 

 

 

CY7C1314AV18

Capacitance[20]

 

 

 

 

 

 

 

Parameter

 

Description

 

Test Conditions

Max.

Unit

CIN

Input Capacitance

 

TA = 25°C, f = 1 MHz,

5

pF

 

 

 

VDD = 1.8V

 

 

CCLK

Clock Input Capacitance

 

6

pF

 

 

 

 

VDDQ = 1.5V

 

 

 

CO

Output Capacitance

 

7

pF

 

 

AC Test Loads and Waveforms

VREF = 0.75V

VREF

 

 

 

 

 

 

 

 

0.75V

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

Z0 = 50Ω

 

 

Device

 

 

 

 

 

 

 

 

 

Under

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test

 

 

 

 

 

 

 

 

 

 

 

 

 

ZQ

RQ = 250Ω

(a)

Note:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREF

 

 

 

 

 

0.75V

 

 

 

 

 

R = 50

Ω

 

 

ALL INPUT PULSES[12]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RL = 50Ω

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.25V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 pF

0.25V

 

 

 

0.75V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Slew Rate = 2V / ns

 

 

 

 

 

 

 

 

 

 

 

 

 

VREF = 0.75V

Under ZQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test

 

 

 

 

 

 

RQ =

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

250Ω

 

 

 

 

 

 

 

 

 

 

 

 

 

INCLUDING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JIG AND

 

 

 

 

 

 

(b)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCOPE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20. Tested initially and after any design or process change that may affect these parameters.

Document #: 38-05497 Rev. *A

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Contents Functional Description FeaturesConfigurations Logic Block Diagram CY7C1310AV18167 MHz 133 MHz Unit Logic Block Diagram CY7C1312AV18Logic Block Diagram CY7C1314AV18 Selection GuideTMS TDI Pin ConfigurationsVSS WPS Pin DefinitionsPin Name Pin Description OperationsTDO for Jtag Negative Output Clock InputNegative Input Clock Input Is referenced with respect toIntroduction RPS WPS Application Example1DLL Comments Write Cycle Descriptions CY7C1314AV18 2BWS Operating Range DC Electrical Characteristics Over the Operating Range9,14AC Electrical Characteristics Over the Operating Range Maximum RatingsThermal Resistance20 Switching Characteristics Over the Operating Range 16,17Input Capacitance TA = 25C, f = 1 MHz VDD = Capacitance20AC Test Loads and Waveforms Parameter Description Test Conditions Max UnitRead/Write/Deselect Sequence PreliminaryIdcode Ieee 1149.1 Serial Boundary Scan JtagExtest Sample ZSAMPLE/PRELOAD BypassEXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram24Parameter Description Test Conditions Min Max Unit TAP Controller Block DiagramParameter Description Min Max Unit TAP AC Switching Characteristics Over the Operating Range26TAP Timing and Test Conditions27 Boundary Scan Order Identification Register DefinitionsScan Register Sizes Instruction Codes10F Ordering Information Package DiagramVBL Document HistoryREV DIM
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