Cypress CY7C1312AV18, CY7C1314AV18, CY7C1310AV18 manual Preliminary, Read/Write/Deselect Sequence

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CY7C1310AV18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PRELIMINARY

 

 

 

 

CY7C1312AV18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1314AV18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Switching Waveforms[21,22,23]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read/Write/Deselect Sequence

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ

 

 

 

 

WRITE

 

 

READ

 

 

WRITE

 

 

 

READ

 

WRITE

 

NOP

 

WRITE

 

NOP

1

 

 

2

 

 

 

3

 

 

4

 

5

 

 

 

 

 

6

 

7

 

8

 

9

10

K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tKL

 

 

 

 

tCYC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tKHKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K

RPS

tSC tHC

WPS

A

A0

A1

 

 

tSA tHA

D D10 D11

Q

tKHCH

A2

A3

A4

A5

tSA tHA

 

 

 

D30

D31

D50

D51

 

tSD

tHD

tSD

 

 

Q00

Q01

 

tCLZ

tDOH

tDOH

tKL

tCO

 

tCO

 

 

A6

D60 D61

tHD

Q20

Q21

Q40

Q41

tCHZ tCQD

C

C

CQ

CQ

tKH

 

 

 

 

 

t CYC

tKHCH

tKHKH

 

 

 

 

 

 

 

tCCQO

tCQOH

tCCQO

tCQOH

DON’T CARE UNDEFINED

Notes:

21.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0 i.e., A0+1.

22.Output are disabled (High-Z) one clock cycle after a NOP.

23.In this example , if address A2=A1,then data Q20=D10 and Q21=D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.,

Document #: 38-05497 Rev. *A

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Contents Features ConfigurationsLogic Block Diagram CY7C1310AV18 Functional DescriptionLogic Block Diagram CY7C1312AV18 Logic Block Diagram CY7C1314AV18Selection Guide 167 MHz 133 MHz UnitPin Configurations VSSTMS TDI Pin Definitions Pin Name Pin DescriptionOperations WPSNegative Output Clock Input Negative Input Clock InputIs referenced with respect to TDO for JtagIntroduction Application Example1 DLLRPS WPS Write Cycle Descriptions CY7C1314AV18 2 BWSComments DC Electrical Characteristics Over the Operating Range9,14 AC Electrical Characteristics Over the Operating RangeMaximum Ratings Operating RangeSwitching Characteristics Over the Operating Range 16,17 Thermal Resistance20Capacitance20 AC Test Loads and WaveformsParameter Description Test Conditions Max Unit Input Capacitance TA = 25C, f = 1 MHz VDD =Preliminary Read/Write/Deselect SequenceIeee 1149.1 Serial Boundary Scan Jtag IdcodeSample Z SAMPLE/PRELOADBypass ExtestTAP Controller State Diagram24 EXIT2-IR UPDATE-DR UPDATE-IRTAP Controller Block Diagram Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics Over the Operating Range26 TAP Timing and Test Conditions27Parameter Description Min Max Unit Identification Register Definitions Scan Register SizesInstruction Codes Boundary Scan Order10F Package Diagram Ordering InformationDocument History REVDIM VBL