Cypress CY7C1356CV25 manual Ieee 1149.1 Serial Boundary Scan Jtag, TAP Controller Block Diagram

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CY7C1354CV25

CY7C1356CV25

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1354CV25/CY7C1356CV25 incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn’t have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 2.5V I/O logic levels.

The CY7C1354CV25/CY7C1356CV25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are inter- nally pulled up and may be unconnected. They may alternately

The ball is pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller Block Diagram

be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.

TAP Controller State Diagram[10]

TDI

Selection Circuitry

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bypass Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

30

29

.

.

.

2

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Selection Circuitry

TDO

1 TEST-LOGIC RESET

0

0 RUN-TEST/

IDLE

1

SELECT

1

SELECT

1

 

DR-SCAN

 

IR-SCAN

 

 

 

0

 

 

0

 

 

1

 

 

1

 

 

 

CAPTURE-DR

 

CAPTURE-IR

 

 

 

0

 

 

0

 

 

SHIFT-DR

0

SHIFT-IR

0

 

 

1

 

 

1

 

 

EXIT1-DR

1

EXIT1-IR

1

 

 

 

 

 

0

 

 

0

 

 

PAUSE-DR

0

PAUSE-IR

0

 

 

1

 

 

1

 

 

0

 

 

0

 

 

 

EXIT2-DR

 

EXIT2-IR

 

 

 

1

 

 

1

 

 

UPDATE-DR

 

UPDATE-IR

 

 

1

0

 

1

0

 

Identification Register

x . . . . . 2 1 0

Boundary Scan Register

TCK

TMS

 

TAP CONTROLLER

 

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating.

At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.

TAP Registers

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used.

Note:

Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction.

10. The 0/1 next to each state represents the value of TMS at the rising edge of the TCK.

 

Document #: 38-05537 Rev. *H

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Contents Functional Description1 FeaturesLogic Block Diagram-CY7C1354CV25 256K x Cypress Semiconductor CorporationSelection Guide Logic Block Diagram-CY7C1356CV25 512K xMaximum Access Time Maximum Operating Current 250 MHz 200 MHz 166 MHz UnitPin Configurations Pin Tqfp Pinout CY7C1354CV25 256K ×Pin Configurations Ball BGA Pinout CY7C1354CV25 256K ×Pin Configurations Ball Fbga Pinout Pin Definitions Single Write Accesses Single Read AccessesBurst Read Accesses Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Function CY7C1354CV25 BW d BW c BW b BW a Sleep ModePartial Write Cycle Description2, 3, 4 Function CY7C1356CV25 BW b BW aTAP Controller State Diagram10 TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetOutput Times TAP TimingParameter Description Min Max Unit Clock Set-up TimesIdentification Register Definitions 5V TAP AC Test Conditions5V TAP AC Output Load Equivalent Scan Register SizesBoundary Scan Exit Order 256K × Bit # Ball IDJ10 Boundary Scan Exit Order 512K ×B10 K10Operating Range Electrical Characteristics Over the Operating Range14Maximum Ratings RangeAC Test Loads and Waveforms Capacitance16Thermal Resistance16 PackageSwitching Characteristics Over the Operating Range 18 250 200 166 Parameter Description Unit Min MaxADV/LD BWX Switching WaveformsRead/Write Timing23, 24 DON’T Care UndefinedCLK CEN ADV/LD BWX NOP, Stall and Deselect CYCLES23, 24ZZ Mode Timing27 DON’T CareOrdering Information CY7C1356CV25-166BZXI Document # 38-05537 Rev. *HCY7C1356CV25-200BZXI Document # 38-05537 Rev. *H CY7C1356CV25-250BZXI Document # 38-05537 Rev. *H Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm 90±0.05Ball Fbga 13 x 15 x 1.4 mm ECN No Issue Date Orig. Description of Change Document History

CY7C1356CV25, CY7C1354CV25 specifications

The Cypress CY7C1354CV25 and CY7C1356CV25 are high-performance, synchronous SRAM (Static Random Access Memory) devices designed for bandwidth-intensive applications. Both components are part of the Cypress family of low-power high-speed SRAMs, making them ideal for use in networking, telecommunications, and high-speed data processing systems.

One of the main features of the CY7C1354CV25 and CY7C1356CV25 is their wide data bus. The CY7C1354CV25 provides a 4 Megabit memory capacity with a 36-bit wide data interface, while the CY7C1356CV25 boosts this to 6 Megabits with a similarly wide data interface. This allows for high data throughput and efficiency in applications where quick access to large data sets is critical.

Both devices offer asynchronous write and synchronous read capabilities, enabling them to support pipelines and burst accesses effectively. The memory can be accessed in a single cycle, which considerably enhances performance in applications that require quick response times, such as high-speed packet processing in routers and switches.

The Cypress SRAMs are built using advanced CMOS technology, enabling low power consumption, which is essential for mobile and battery-operated devices. Their operating voltage range, typically between 2.7V and 3.6V, contributes to the low power profile while providing a high level of performance.

Moreover, both devices support a wide temperature range, making them suitable for industrial applications. They can operate in environments from -40°C to +125°C, ensuring reliability and performance under varying conditions. This makes the CY7C1354CV25 and CY7C1356CV25 particularly valuable for automotive and aerospace applications where temperature extremes can be encountered.

Cypress has enhanced the reliability of these SRAMs with features such as built-in error detection and correction capabilities. This ensures data integrity, which is crucial for mission-critical applications.

In summary, the Cypress CY7C1354CV25 and CY7C1356CV25 ensure tight integration of high capacity, speed, and reliability. With their advanced synchronous architecture, low power consumption, and broad temperature range, they represent an excellent choice for applications that demand high performance in challenging environments. These SRAM devices continue to meet the needs of modern electronic designs, making them a trusted solution in the industry.
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