Cypress CY7C1356CV25, CY7C1354CV25 manual Switching Characteristics Over the Operating Range 18

Page 18

CY7C1354CV25

CY7C1356CV25

Switching Characteristics Over the Operating Range [18, 19]

 

 

 

 

 

 

 

 

 

 

–250

–200

–166

 

Parameter

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

Unit

 

 

 

 

 

 

 

 

Min.

Max.

Min.

Max.

Min.

Max.

 

 

 

 

 

 

 

 

 

 

tPower[17]

 

VCC (typical) to the First Access Read or Write

1

 

1

 

1

 

ms

Clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCYC

 

Clock Cycle Time

4.0

 

5

 

6

 

ns

FMAX

 

Maximum Operating Frequency

 

250

 

200

 

166

MHz

tCH

 

Clock HIGH

1.8

 

2.0

 

2.4

 

ns

tCL

 

Clock LOW

1.8

 

2.0

 

2.4

 

ns

Output Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCO

 

Data Output Valid after CLK Rise

 

2.8

 

3.2

 

3.5

ns

tEOV

 

 

 

LOW to Output Valid

 

2.8

 

3.2

 

3.5

ns

OE

 

 

 

tDOH

 

Data Output Hold after CLK Rise

1.25

 

1.5

 

1.5

 

ns

tCHZ

 

Clock to High-Z[20, 21, 22]

1.25

2.8

1.5

3.2

1.5

3.5

ns

tCLZ

 

Clock to Low-Z[20, 21, 22]

1.25

 

1.5

 

1.5

 

ns

tEOHZ

 

 

 

HIGH to Output High-Z[20, 21, 22]

 

2.8

 

3.2

 

3.5

ns

OE

 

 

 

t

 

 

 

LOW to Output Low-Z[20, 21, 22]

0

 

0

 

0

 

ns

OE

 

 

 

EOLZ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Set-up Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAS

 

Address Set-up before CLK Rise

1.4

 

1.5

 

1.5

 

ns

tDS

 

Data Input Set-up before CLK Rise

1.4

 

1.5

 

1.5

 

ns

tCENS

 

 

 

 

 

 

Set-up before CLK Rise

1.4

 

1.5

 

1.5

 

ns

CEN

 

 

 

tWES

 

 

 

 

 

 

 

x Set-up before CLK Rise

1.4

 

1.5

 

1.5

 

ns

WE,

BW

 

 

 

tALS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADV/LD

Set-up before CLK Rise

1.4

 

1.5

 

1.5

 

ns

tCES

 

Chip Select Set-up

1.4

 

1.5

 

1.5

 

ns

Hold Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAH

 

Address Hold after CLK Rise

0.4

 

0.5

 

0.5

 

ns

tDH

 

Data Input Hold after CLK Rise

0.4

 

0.5

 

0.5

 

ns

tCENH

 

 

 

 

Hold after CLK Rise

0.4

 

0.5

 

0.5

 

ns

CEN

 

 

 

tWEH

 

 

 

 

 

 

 

x Hold after CLK Rise

0.4

 

0.5

 

0.5

 

ns

WE,

BW

 

 

 

tALH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADV/LD

Hold after CLK Rise

0.4

 

0.5

 

0.5

 

ns

tCEH

 

Chip Select Hold after CLK Rise

0.4

 

0.5

 

0.5

 

ns

Notes:

17.This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be initiated.

18.Timing reference level is when VDDQ = 2.5V.

19.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

20.tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

21.At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

22.This parameter is sampled and not 100% tested.

Document #: 38-05537 Rev. *H

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Contents Functional Description1 FeaturesLogic Block Diagram-CY7C1354CV25 256K x Cypress Semiconductor CorporationSelection Guide Logic Block Diagram-CY7C1356CV25 512K xMaximum Access Time Maximum Operating Current 250 MHz 200 MHz 166 MHz UnitPin Configurations Pin Tqfp Pinout CY7C1354CV25 256K ×Pin Configurations Ball BGA Pinout CY7C1354CV25 256K ×Pin Configurations Ball Fbga Pinout Pin Definitions Single Write Accesses Single Read AccessesBurst Read Accesses Functional OverviewInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Function CY7C1354CV25 BW d BW c BW b BW a Sleep ModePartial Write Cycle Description2, 3, 4 Function CY7C1356CV25 BW b BW aTAP Controller Block Diagram TAP Controller State Diagram10Ieee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetOutput Times TAP TimingParameter Description Min Max Unit Clock Set-up TimesIdentification Register Definitions 5V TAP AC Test Conditions5V TAP AC Output Load Equivalent Scan Register SizesBoundary Scan Exit Order 256K × Bit # Ball IDJ10 Boundary Scan Exit Order 512K ×B10 K10Operating Range Electrical Characteristics Over the Operating Range14Maximum Ratings RangeAC Test Loads and Waveforms Capacitance16Thermal Resistance16 PackageSwitching Characteristics Over the Operating Range 18 250 200 166 Parameter Description Unit Min MaxADV/LD BWX Switching WaveformsRead/Write Timing23, 24 DON’T Care UndefinedCLK CEN ADV/LD BWX NOP, Stall and Deselect CYCLES23, 24ZZ Mode Timing27 DON’T CareOrdering Information CY7C1356CV25-166BZXI Document # 38-05537 Rev. *HCY7C1356CV25-200BZXI Document # 38-05537 Rev. *H CY7C1356CV25-250BZXI Document # 38-05537 Rev. *H Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm 90±0.05Ball Fbga 13 x 15 x 1.4 mm ECN No Issue Date Orig. Description of Change Document History

CY7C1356CV25, CY7C1354CV25 specifications

The Cypress CY7C1354CV25 and CY7C1356CV25 are high-performance, synchronous SRAM (Static Random Access Memory) devices designed for bandwidth-intensive applications. Both components are part of the Cypress family of low-power high-speed SRAMs, making them ideal for use in networking, telecommunications, and high-speed data processing systems.

One of the main features of the CY7C1354CV25 and CY7C1356CV25 is their wide data bus. The CY7C1354CV25 provides a 4 Megabit memory capacity with a 36-bit wide data interface, while the CY7C1356CV25 boosts this to 6 Megabits with a similarly wide data interface. This allows for high data throughput and efficiency in applications where quick access to large data sets is critical.

Both devices offer asynchronous write and synchronous read capabilities, enabling them to support pipelines and burst accesses effectively. The memory can be accessed in a single cycle, which considerably enhances performance in applications that require quick response times, such as high-speed packet processing in routers and switches.

The Cypress SRAMs are built using advanced CMOS technology, enabling low power consumption, which is essential for mobile and battery-operated devices. Their operating voltage range, typically between 2.7V and 3.6V, contributes to the low power profile while providing a high level of performance.

Moreover, both devices support a wide temperature range, making them suitable for industrial applications. They can operate in environments from -40°C to +125°C, ensuring reliability and performance under varying conditions. This makes the CY7C1354CV25 and CY7C1356CV25 particularly valuable for automotive and aerospace applications where temperature extremes can be encountered.

Cypress has enhanced the reliability of these SRAMs with features such as built-in error detection and correction capabilities. This ensures data integrity, which is crucial for mission-critical applications.

In summary, the Cypress CY7C1354CV25 and CY7C1356CV25 ensure tight integration of high capacity, speed, and reliability. With their advanced synchronous architecture, low power consumption, and broad temperature range, they represent an excellent choice for applications that demand high performance in challenging environments. These SRAM devices continue to meet the needs of modern electronic designs, making them a trusted solution in the industry.
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