Cypress CY7C1354CV25, CY7C1356CV25 5V TAP AC Test Conditions, 5V TAP AC Output Load Equivalent

Page 13

CY7C1354CV25

CY7C1356CV25

2.5V TAP AC Test Conditions

Input pulse levels

VSS to 2.5V

Input rise and fall time

1 ns

Input timing reference levels

1.25V

Output reference levels

1.25V

Test load termination supply voltage

1.25V

2.5V TAP AC Output Load Equivalent

1.25V

50Ω

TDO

ZO= 50Ω

 

 

 

 

20pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)[13]

Parameter

Description

 

Test Conditions

Min.

Max.

Unit

VOH1

Output HIGH Voltage

IOH = –1.0 mA, VDDQ = 2.5V

2.0

 

V

VOH2

Output HIGH Voltage

IOH = –100 µA,VDDQ = 2.5V

2.1

 

V

VOL1

Output LOW Voltage

IOL = 8.0 mA, VDDQ = 2.5V

 

0.4

V

VOL2

Output LOW Voltage

IOL = 100 µA

 

VDDQ = 2.5V

 

0.2

V

VIH

Input HIGH Voltage

 

 

VDDQ = 2.5V

1.7

VDD + 0.3

V

VIL

Input LOW Voltage

 

 

VDDQ = 2.5V

–0.3

0.7

V

IX

Input Load Current

GND < VIN < VDDQ

 

–5

5

µA

Identification Register Definitions

Instruction Field

CY7C1354CV25

CY7C1356CV25

Description

Revision Number (31:29)

000

000

Reserved for version number.

 

 

 

 

Cypress Device ID (28:12)

01011001000100110

01011001000010110

Reserved for future use.

 

 

 

 

Cypress JEDEC ID (11:1)

00000110100

00000110100

Allows unique identification of SRAM vendor.

 

 

 

 

ID Register Presence (0)

1

1

Indicate the presence of an ID register.

 

 

 

 

Scan Register Sizes

 

 

 

Register Name

Bit Size (x36)

Bit Size (x18)

Instruction

3

3

 

 

 

Bypass

1

1

 

 

 

ID

32

32

 

 

 

Boundary Scan Order (119-ball BGA

69

69

package)

 

 

Boundary Scan Order (165-ball FBGA

69

69

package)

 

 

Identification Codes

 

 

 

Instruction

Code

Description

 

 

EXTEST

000

Captures the Input/Output ring contents. Places the boundary scan register between the TDI and

 

 

 

TDO. Forces all SRAM outputs to High-Z state.

 

 

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO. This

 

 

 

operation does not affect SRAM operation.

 

 

SAMPLE Z

010

Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.

 

 

 

Forces all SRAM output drivers to a High-Z state.

 

 

RESERVED

011

Do Not Use: This instruction is reserved for future use.

 

 

 

 

 

 

SAMPLE/PRELOAD

100

Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO.

 

 

 

Does not affect the SRAM operation.

 

 

RESERVED

101

Do Not Use: This instruction is reserved for future use.

 

 

 

 

 

 

 

RESERVED

110

Do Not Use: This instruction is reserved for future use.

 

 

 

 

 

 

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.

 

 

 

 

 

 

Note:

 

 

 

 

13. All voltages referenced to VSS (GND).

 

Document #: 38-05537 Rev. *H

Page 13 of 28

[+] Feedback

Page 12 Page 14
Image 13
Page 12 Page 14
Contents Logic Block Diagram-CY7C1354CV25 256K x FeaturesFunctional Description1 Cypress Semiconductor CorporationMaximum Access Time Maximum Operating Current Logic Block Diagram-CY7C1356CV25 512K xSelection Guide 250 MHz 200 MHz 166 MHz UnitCY7C1354CV25 256K × Pin Configurations Pin Tqfp PinoutCY7C1354CV25 256K × Pin Configurations Ball BGA PinoutPin Configurations Ball Fbga Pinout Pin Definitions Burst Read Accesses Single Read AccessesSingle Write Accesses Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Partial Write Cycle Description2, 3, 4 Sleep ModeFunction CY7C1354CV25 BW d BW c BW b BW a Function CY7C1356CV25 BW b BW aTAP Controller State Diagram10 TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterParameter Description Min Max Unit Clock TAP TimingOutput Times Set-up Times5V TAP AC Output Load Equivalent 5V TAP AC Test ConditionsIdentification Register Definitions Scan Register SizesBit # Ball ID Boundary Scan Exit Order 256K ×B10 Boundary Scan Exit Order 512K ×J10 K10Maximum Ratings Electrical Characteristics Over the Operating Range14Operating Range RangeThermal Resistance16 Capacitance16AC Test Loads and Waveforms Package250 200 166 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 18Read/Write Timing23, 24 Switching WaveformsADV/LD BWX DON’T Care UndefinedNOP, Stall and Deselect CYCLES23, 24 CLK CEN ADV/LD BWXDON’T Care ZZ Mode Timing27CY7C1356CV25-166BZXI Document # 38-05537 Rev. *H Ordering InformationCY7C1356CV25-200BZXI Document # 38-05537 Rev. *H CY7C1356CV25-250BZXI Document # 38-05537 Rev. *H Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams90±0.05 Ball BGA 14 x 22 x 2.4 mmBall Fbga 13 x 15 x 1.4 mm Document History ECN No Issue Date Orig. Description of Change

CY7C1356CV25, CY7C1354CV25 specifications

The Cypress CY7C1354CV25 and CY7C1356CV25 are high-performance, synchronous SRAM (Static Random Access Memory) devices designed for bandwidth-intensive applications. Both components are part of the Cypress family of low-power high-speed SRAMs, making them ideal for use in networking, telecommunications, and high-speed data processing systems.

One of the main features of the CY7C1354CV25 and CY7C1356CV25 is their wide data bus. The CY7C1354CV25 provides a 4 Megabit memory capacity with a 36-bit wide data interface, while the CY7C1356CV25 boosts this to 6 Megabits with a similarly wide data interface. This allows for high data throughput and efficiency in applications where quick access to large data sets is critical.

Both devices offer asynchronous write and synchronous read capabilities, enabling them to support pipelines and burst accesses effectively. The memory can be accessed in a single cycle, which considerably enhances performance in applications that require quick response times, such as high-speed packet processing in routers and switches.

The Cypress SRAMs are built using advanced CMOS technology, enabling low power consumption, which is essential for mobile and battery-operated devices. Their operating voltage range, typically between 2.7V and 3.6V, contributes to the low power profile while providing a high level of performance.

Moreover, both devices support a wide temperature range, making them suitable for industrial applications. They can operate in environments from -40°C to +125°C, ensuring reliability and performance under varying conditions. This makes the CY7C1354CV25 and CY7C1356CV25 particularly valuable for automotive and aerospace applications where temperature extremes can be encountered.

Cypress has enhanced the reliability of these SRAMs with features such as built-in error detection and correction capabilities. This ensures data integrity, which is crucial for mission-critical applications.

In summary, the Cypress CY7C1354CV25 and CY7C1356CV25 ensure tight integration of high capacity, speed, and reliability. With their advanced synchronous architecture, low power consumption, and broad temperature range, they represent an excellent choice for applications that demand high performance in challenging environments. These SRAM devices continue to meet the needs of modern electronic designs, making them a trusted solution in the industry.
Top Page Image Contents