Cypress CY7C1354CV25, CY7C1356CV25 manual Boundary Scan Exit Order 512K ×, B10, J10, K10, P10

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CY7C1354CV25

CY7C1356CV25

Boundary Scan Exit Order (512K × 18)

Bit #

119-ball ID

165-ball ID

1

K4

B6

2

H4

B7

3

M4

A7

4

F4

B8

5

B4

A8

6

G4

A9

7

C3

B10

8

B3

A10

9

T2

A11

10

Not Bonded

Not Bonded

 

(Preset to 0)

(Preset to 0)

11

Not Bonded

Not Bonded

 

(Preset to 0)

(Preset to 0)

12

Not Bonded

Not Bonded

 

(Preset to 0)

(Preset to 0)

13

D6

C11

14

E7

D11

15

F6

E11

16

G7

F11

17

H6

G11

18

T7

H11

19

K7

J10

20

L6

K10

21

N6

L10

22

P7

M10

23

Not Bonded

Not Bonded

 

(Preset to 0)

(Preset to 0)

24

Not Bonded

Not Bonded

 

(Preset to 0)

(Preset to 0)

25

Not Bonded

Not Bonded

 

(Preset to 0)

(Preset to 0)

26

Not Bonded

Not Bonded

 

(Preset to 0)

(Preset to 0)

27

Not Bonded

Not Bonded

 

(Preset to 0)

(Preset to 0)

28

T6

R11

29

A3

R10

30

C5

P10

31

B5

R9

32

A5

P9

33

C6

R8

34

A6

P8

35

P4

R6

36

N4

P6

37

R6

R4

38

T5

P4

39

T3

R3

40

R2

P3

41

R3

R1

Boundary Scan Exit Order (512K × 18) (continued)

Bit #

119-ball ID

165-ball ID

42

Not Bonded

Not Bonded

 

(Preset to 0)

(Preset to 0)

43

Not Bonded

Not Bonded

 

(Preset to 0)

(Preset to 0)

44

Not Bonded

Not Bonded

 

(Preset to 0)

(Preset to 0)

45

Not Bonded

Not Bonded

 

(Preset to 0)

(Preset to 0)

46

P2

N1

47

N1

M1

48

M2

L1

49

L1

K1

50

K2

J1

51

Not Bonded

Not Bonded

 

(Preset to 1)

(Preset to 1)

52

H1

G2

53

G2

F2

54

E2

E2

55

D1

D2

56

Not Bonded

Not Bonded

 

(Preset to 0)

(Preset to 0)

57

Not Bonded

Not Bonded

 

(Preset to 0)

(Preset to 0)

58

Not Bonded

Not Bonded

 

(Preset to 0)

(Preset to 0)

59

Not Bonded

Not Bonded

 

(Preset to 0)

(Preset to 0)

60

Not Bonded

Not Bonded

 

(Preset to 0)

(Preset to 0)

61

C2

B2

62

A2

A2

63

E4

A3

64

B2

B3

65

Not Bonded

Not Bonded

 

(Preset to 0

(Preset to 0)

66

G3

Not Bonded

 

 

(Preset to 0)

67

Not Bonded

A4

 

(Preset to 0

 

68

L5

B5

69

B6

A6

69

B6

A6

69

B6

A6

68

L5

B5

69

B6

A6

66

G3

Not Bonded

 

 

(Preset to 0)

67

Not Bonded

A4

 

(Preset to 0

 

68

L5

B5

69

B6

A6

Document #: 38-05537 Rev. *H

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram-CY7C1354CV25 256K x Functional Description1250 MHz 200 MHz 166 MHz Unit Logic Block Diagram-CY7C1356CV25 512K xMaximum Access Time Maximum Operating Current Selection GuideCY7C1354CV25 256K × Pin Configurations Pin Tqfp PinoutCY7C1354CV25 256K × Pin Configurations Ball BGA PinoutPin Configurations Ball Fbga Pinout Pin Definitions Functional Overview Single Read AccessesBurst Read Accesses Single Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Function CY7C1356CV25 BW b BW a Sleep ModePartial Write Cycle Description2, 3, 4 Function CY7C1354CV25 BW d BW c BW b BW aTAP Controller Block Diagram TAP Controller State Diagram10Ieee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterSet-up Times TAP TimingParameter Description Min Max Unit Clock Output TimesScan Register Sizes 5V TAP AC Test Conditions5V TAP AC Output Load Equivalent Identification Register DefinitionsBit # Ball ID Boundary Scan Exit Order 256K ×K10 Boundary Scan Exit Order 512K ×B10 J10Range Electrical Characteristics Over the Operating Range14Maximum Ratings Operating RangePackage Capacitance16Thermal Resistance16 AC Test Loads and Waveforms250 200 166 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 18DON’T Care Undefined Switching WaveformsRead/Write Timing23, 24 ADV/LD BWXNOP, Stall and Deselect CYCLES23, 24 CLK CEN ADV/LD BWXDON’T Care ZZ Mode Timing27CY7C1356CV25-166BZXI Document # 38-05537 Rev. *H Ordering InformationCY7C1356CV25-200BZXI Document # 38-05537 Rev. *H CY7C1356CV25-250BZXI Document # 38-05537 Rev. *H Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams90±0.05 Ball BGA 14 x 22 x 2.4 mmBall Fbga 13 x 15 x 1.4 mm Document History ECN No Issue Date Orig. Description of Change

CY7C1356CV25, CY7C1354CV25 specifications

The Cypress CY7C1354CV25 and CY7C1356CV25 are high-performance, synchronous SRAM (Static Random Access Memory) devices designed for bandwidth-intensive applications. Both components are part of the Cypress family of low-power high-speed SRAMs, making them ideal for use in networking, telecommunications, and high-speed data processing systems.

One of the main features of the CY7C1354CV25 and CY7C1356CV25 is their wide data bus. The CY7C1354CV25 provides a 4 Megabit memory capacity with a 36-bit wide data interface, while the CY7C1356CV25 boosts this to 6 Megabits with a similarly wide data interface. This allows for high data throughput and efficiency in applications where quick access to large data sets is critical.

Both devices offer asynchronous write and synchronous read capabilities, enabling them to support pipelines and burst accesses effectively. The memory can be accessed in a single cycle, which considerably enhances performance in applications that require quick response times, such as high-speed packet processing in routers and switches.

The Cypress SRAMs are built using advanced CMOS technology, enabling low power consumption, which is essential for mobile and battery-operated devices. Their operating voltage range, typically between 2.7V and 3.6V, contributes to the low power profile while providing a high level of performance.

Moreover, both devices support a wide temperature range, making them suitable for industrial applications. They can operate in environments from -40°C to +125°C, ensuring reliability and performance under varying conditions. This makes the CY7C1354CV25 and CY7C1356CV25 particularly valuable for automotive and aerospace applications where temperature extremes can be encountered.

Cypress has enhanced the reliability of these SRAMs with features such as built-in error detection and correction capabilities. This ensures data integrity, which is crucial for mission-critical applications.

In summary, the Cypress CY7C1354CV25 and CY7C1356CV25 ensure tight integration of high capacity, speed, and reliability. With their advanced synchronous architecture, low power consumption, and broad temperature range, they represent an excellent choice for applications that demand high performance in challenging environments. These SRAM devices continue to meet the needs of modern electronic designs, making them a trusted solution in the industry.