Cypress CY7C1356CV25 manual Document History, ECN No Issue Date Orig. Description of Change

Page 28

CY7C1354CV25

CY7C1356CV25

Document History Page

Document Title: CY7C1354CV25/CY7C1356CV25 9-Mbit (256K x 36/512K x 18)

Pipelined SRAM with NoBL™ Architecture

Document Number: 38-05537

REV.

ECN No.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

 

**

242032

See ECN

RKF

New data sheet

 

 

 

 

 

*A

278969

See ECN

RKF

Changed Boundary Scan order to match the B Rev of these devices

 

 

 

 

 

*B

284929

See ECN

RKF

Included DC Characteristics Table

 

 

 

VBL

Changed ISB1 and ISB3 from DC Characteristic table as follows:

 

 

 

 

ISB1: 225 MHz -> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA

 

 

 

 

ISB3: 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA

 

 

 

 

Changed IDDZZ to 50mA.

 

 

 

 

Added BG and BZ pkg lead-free part numbers to ordering info section.

*C

323636

See ECN

PCI

Changed frequency of 225 MHz into 250 MHz

 

 

 

 

Added tCYC of 4.0 ns for 250 MHz

 

 

 

 

Changed ΘJA and ΘJC for TQFP Package from 25 and 9 °C/W to 29.41 and

 

 

 

 

6.13 °C/W respectively

 

 

 

 

Changed ΘJA and ΘJC for BGA Package from 25 and 6 °C/W to 34.1 and

 

 

 

 

14.0 °C/W respectively

 

 

 

 

Changed ΘJA and ΘJC for FBGA Package from 27 and 6 °C/W to 16.8 and

 

 

 

 

3.0 °C/W respectively

 

 

 

 

Modified address expansion as per JEDEC Standard

 

 

 

 

Removed comment of Lead-free BG and BZ packages availability

*D

332879

See ECN

PCI

Unshaded 200 and 166 MHz speed bin in the AC/DC Table and Selection

 

 

 

 

Guide

 

 

 

 

Added Address Expansion pins in the Pin Definition Table

 

 

 

 

Removed description of Extest Output Bus Tri-state on page # 11

 

 

 

 

Modified VOL, VOH test conditions

 

 

 

 

Updated Ordering Information Table

*E

357258

See ECN

PCI

Changed from Preliminary to Final

 

 

 

 

Changed ISB2 from 35 to 40 mA

 

 

 

 

Removed Shading on 250MHz Speed Bin in Selection Guide and AC/DC

 

 

 

 

Table

 

 

 

 

Updated Ordering Information Table

*F

377095

See ECN

PCI

Modified test condition in note# 15 from VDDQ < VDD to VDDQ ≤ VDD

*G

408298

See ECN

RXU

Changed address of Cypress Semiconductor Corporation on Page# 1 from

 

 

 

 

“3901 North First Street” to “198 Champion Court”

 

 

 

 

Changed three-state to tri-state.

 

 

 

 

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in

 

 

 

 

the Electrical Characteristics Table.

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

Information table.

 

 

 

 

Updated the Ordering Information Table.

*H

501793

See ECN

VKN

Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND

 

 

 

 

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP

 

 

 

 

AC Switching Characteristics table.

 

 

 

 

Updated the Ordering Information table.

Document #: 38-05537 Rev. *H

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Contents Features Logic Block Diagram-CY7C1354CV25 256K xFunctional Description1 Cypress Semiconductor CorporationLogic Block Diagram-CY7C1356CV25 512K x Maximum Access Time Maximum Operating CurrentSelection Guide 250 MHz 200 MHz 166 MHz UnitPin Configurations Pin Tqfp Pinout CY7C1354CV25 256K ×Pin Configurations Ball BGA Pinout CY7C1354CV25 256K ×Pin Configurations Ball Fbga Pinout Pin Definitions Single Read Accesses Burst Read AccessesSingle Write Accesses Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Sleep Mode Partial Write Cycle Description2, 3, 4Function CY7C1354CV25 BW d BW c BW b BW a Function CY7C1356CV25 BW b BW aTAP Controller State Diagram10 TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetTAP Timing Parameter Description Min Max Unit ClockOutput Times Set-up Times5V TAP AC Test Conditions 5V TAP AC Output Load EquivalentIdentification Register Definitions Scan Register SizesBoundary Scan Exit Order 256K × Bit # Ball IDBoundary Scan Exit Order 512K × B10J10 K10Electrical Characteristics Over the Operating Range14 Maximum RatingsOperating Range RangeCapacitance16 Thermal Resistance16AC Test Loads and Waveforms PackageSwitching Characteristics Over the Operating Range 18 250 200 166 Parameter Description Unit Min MaxSwitching Waveforms Read/Write Timing23, 24ADV/LD BWX DON’T Care UndefinedCLK CEN ADV/LD BWX NOP, Stall and Deselect CYCLES23, 24ZZ Mode Timing27 DON’T CareOrdering Information CY7C1356CV25-166BZXI Document # 38-05537 Rev. *HCY7C1356CV25-200BZXI Document # 38-05537 Rev. *H CY7C1356CV25-250BZXI Document # 38-05537 Rev. *H Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm 90±0.05Ball Fbga 13 x 15 x 1.4 mm ECN No Issue Date Orig. Description of Change Document History

CY7C1356CV25, CY7C1354CV25 specifications

The Cypress CY7C1354CV25 and CY7C1356CV25 are high-performance, synchronous SRAM (Static Random Access Memory) devices designed for bandwidth-intensive applications. Both components are part of the Cypress family of low-power high-speed SRAMs, making them ideal for use in networking, telecommunications, and high-speed data processing systems.

One of the main features of the CY7C1354CV25 and CY7C1356CV25 is their wide data bus. The CY7C1354CV25 provides a 4 Megabit memory capacity with a 36-bit wide data interface, while the CY7C1356CV25 boosts this to 6 Megabits with a similarly wide data interface. This allows for high data throughput and efficiency in applications where quick access to large data sets is critical.

Both devices offer asynchronous write and synchronous read capabilities, enabling them to support pipelines and burst accesses effectively. The memory can be accessed in a single cycle, which considerably enhances performance in applications that require quick response times, such as high-speed packet processing in routers and switches.

The Cypress SRAMs are built using advanced CMOS technology, enabling low power consumption, which is essential for mobile and battery-operated devices. Their operating voltage range, typically between 2.7V and 3.6V, contributes to the low power profile while providing a high level of performance.

Moreover, both devices support a wide temperature range, making them suitable for industrial applications. They can operate in environments from -40°C to +125°C, ensuring reliability and performance under varying conditions. This makes the CY7C1354CV25 and CY7C1356CV25 particularly valuable for automotive and aerospace applications where temperature extremes can be encountered.

Cypress has enhanced the reliability of these SRAMs with features such as built-in error detection and correction capabilities. This ensures data integrity, which is crucial for mission-critical applications.

In summary, the Cypress CY7C1354CV25 and CY7C1356CV25 ensure tight integration of high capacity, speed, and reliability. With their advanced synchronous architecture, low power consumption, and broad temperature range, they represent an excellent choice for applications that demand high performance in challenging environments. These SRAM devices continue to meet the needs of modern electronic designs, making them a trusted solution in the industry.
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