Cypress CY7C1470BV25, CY7C1474BV25, CY7C1472BV25 manual TAP Timing

Page 14

CY7C1470BV25 CY7C1472BV25, CY7C1474BV25

possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register.

After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls.

Note that since the PRELOAD part of the command is not imple- mented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction has the same effect as the Pause-DR command.

Figure 4. TAP Timing

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

1		2
Test Clock
(TCK )				tTH
				tTH

tTM SS			tTM SH

Test M ode Select (TM S)

tTDIS tTDIH

Test Data-In (TDI)

Test Data-Out (TDO)

3	4	5	6
tTL	tCY C

tTDOV

tTDOX

DON’T CA RE

UNDEFINED

Document #: 001-15032 Rev. *D

Page 14 of 29

[+] Feedback

Image 14

Contents Selection Guide FeaturesFunctional Description Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1470BV25 2M x Logic Block Diagram CY7C1472BV25 4M xLogic Block Diagram CY7C1474BV25 1M x ADV/LDPin Configurations Pin Tqfp PinoutTDI TDO CENNC/1G CE2 CLK ModeBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1474BV25 1M × Dqpx Pin Definitions Pin Name IO Type Pin DescriptionADV/LD TDIFunctional Overview Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsBurst Write Accesses Used Truth TableAddress Operation Function CY7C1472BV25 Partial Write Cycle DescriptionFunction CY7C1470BV25 Function CY7C1474BV25TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set TAP Timing Hold Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock GND ≤ VI ≤ Vddq TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Scan Register Sizes Register Name Bit SizeIdentification Codes Instruction Description Boundary Scan Exit Order 2M x Bit # Ball IDBit # Ball ID Boundary Scan Exit Order 4M xBoundary Scan Exit Order 1M x 10 R1 11 R2 12 R3 13 P2Operating Range Electrical CharacteristicsMaximum Ratings Range AmbientAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description Test Conditions Tqfp Fbga UnitParameter Description 250 200 167 Unit Min Max Switching CharacteristicsSetup Times Output TimesData Switching WaveformsADV/LD Address A3 A4NOP, Stall and Deselect Cycles Ordering Information 250 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. of Change Description of Change Document History