Cypress CY7C1472BV25, CY7C1474BV25, CY7C1470BV25 manual 5V TAP AC Test Conditions, GND ≤ VI ≤ Vddq

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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25

2.5V TAP AC Test Conditions

Input pulse levels	VSS to 2.5V
Input rise and fall time	1 ns
Input timing reference levels	1.25V
Output reference levels	1.25V
Test load termination supply voltage	1.25V

Figure 5. 2.5V TAP AC Output Load Equivalent

1.25V

50Ω

TDO

ZO= 50Ω							20pF

TAP DC Electrical Characteristics And Operating Conditions

(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)[11]

Parameter	Description	Test Conditions	Min	Max	Unit
VOH1	Output HIGH Voltage	IOH = –1.0 mA, VDDQ = 2.5V	1.7		V
VOH2	Output HIGH Voltage	IOH = –100 μA, VDDQ = 2.5V	2.1		V
VOL1	Output LOW Voltage	IOL = 1.0 mA, VDDQ = 2.5V		0.4	V
VOL2	Output LOW Voltage	IOL = 100 μA, VDDQ = 2.5V		0.2	V
VIH	Input HIGH Voltage	VDDQ = 2.5V	1.7	VDD + 0.3	V
VIL	Input LOW Voltage	VDDQ = 2.5V	–0.3	0.7	V
IX	Input Load Current	GND ≤ VI ≤ VDDQ	–5	5	μA

Table 6. Identification Register Definitions

	Instruction Field	CY7C1470BV25	CY7C1472BV25	CY7C1474BV25	Description
	Instruction Field	(2M x 36)	(4M x 18)	(1M x 72)	Description
		(2M x 36)	(4M x 18)	(1M x 72)
	Revision Number (31:29)	000	000	000	Describes the version number

	Device Depth (28:24)	01011	01011	01011	Reserved for internal use

	Architecture/Memory Type(23:18)	001000	001000	001000	Defines memory type and archi-
					tecture
	Bus Width/Density(17:12)	100100	010100	110100	Defines width and density

	Cypress JEDEC ID Code (11:1)	00000110100	00000110100	00000110100	Allows unique identification of
					SRAM vendor
	ID Register Presence Indicator (0)	1	1	1	Indicates the presence of an ID
					register

Table 7. Scan Register Sizes

Register Name	Bit Size (x36)	Bit Size (x18)	Bit Size (x72)
Instruction	3	3	3

Bypass	1	1	1

ID	32	32	32

Boundary Scan Order–165FBGA	71	52	–

Boundary Scan Order–209BGA	–	–	110

Note

11. All voltages refer to VSS (GND).

Document #: 001-15032 Rev. *D

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Contents Features Functional DescriptionSelection Guide Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1470BV25 2M x Logic Block Diagram CY7C1472BV25 4M xLogic Block Diagram CY7C1474BV25 1M x ADV/LDPin Configurations Pin Tqfp PinoutCEN NC/1G CE2 CLKTDI TDO ModeBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1474BV25 1M × Pin Definitions Pin Name IO Type Pin Description ADV/LDDqpx TDIFunctional Overview Burst Write Accesses ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Address Operation Truth TableUsed Partial Write Cycle Description Function CY7C1470BV25Function CY7C1472BV25 Function CY7C1474BV25TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set TAP Timing Parameter Description Min Max Unit Clock TAP AC Switching CharacteristicsHold Times TAP DC Electrical Characteristics And Operating Conditions 5V TAP AC Test ConditionsGND ≤ VI ≤ Vddq Scan Register Sizes Register Name Bit SizeIdentification Codes Instruction Description Boundary Scan Exit Order 2M x Bit # Ball IDBoundary Scan Exit Order 4M x Boundary Scan Exit Order 1M xBit # Ball ID 10 R1 11 R2 12 R3 13 P2Electrical Characteristics Maximum RatingsOperating Range Range AmbientCapacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Tqfp Fbga UnitSwitching Characteristics Setup TimesParameter Description 250 200 167 Unit Min Max Output TimesSwitching Waveforms ADV/LD AddressData A3 A4NOP, Stall and Deselect Cycles Ordering Information 250 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. of Change Description of Change Document History