Cypress CY7C1472BV25 Maximum Ratings, Operating Range, Electrical Characteristics, Range Ambient

CY7C1470BV25 CY7C1472BV25, CY7C1474BV25

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature		–65°C to +150°C
Ambient Temperature with
Power Applied		–55°C to +125°C
Supply Voltage on VDD Relative to GND		–0.5V to +3.6V
Supply Voltage on VDDQ Relative to GND		–0.5V to +VDD
DC to Outputs in Tri-State	–0.5V to VDDQ + 0.5V
DC Input Voltage	–0.5V to VDD + 0.5V

Current into Outputs (LOW)			20 mA
Static Discharge Voltage			> 2001V
(MIL-STD-883, Method 3015)
Latch up Current			> 200 mA
Operating Range
Range	Ambient	VDD	VDDQ
	Temperature
Commercial	0°C to +70°C	2.5V –5%/+5%	2.5V–5% to
			VDD
Industrial	–40°C to +85°C

Electrical Characteristics

Over the Operating Range[12, 13]

Parameter	Description	Test Conditions		Min	Max	Unit
VDD	Power Supply Voltage			2.375	2.625	V
VDDQ	IO Supply Voltage	For 2.5V IO		2.375	VDD	V
VOH	Output HIGH Voltage	For 2.5V IO, IOH= −1.0 mA		2.0		V
VOL	Output LOW Voltage	For 2.5V IO, IOL= 1.0 mA			0.4	V
VIH	Input HIGH Voltage[12]	For 2.5V IO		1.7	VDD + 0.3V	V
VIL	Input LOW Voltage[12]	For 2.5V IO		–0.3	0.7	V
IX	Input Leakage Current	GND ≤ VI ≤ VDDQ		–5	5	μA
	except ZZ and MODE
	Input Current of MODE	Input = VSS		–30		μA
		Input = VDD			5	μA
	Input Current of ZZ	Input = VSS		–5		μA
		Input = VDD			30	μA
IOZ	Output Leakage Current	GND ≤ VI ≤ VDDQ, Output Disabled		–5	5	μA
IDD [14]	VDD Operating Supply	VDD = Max, IOUT = 0 mA,	4.0-ns cycle, 250 MHz		450	mA
		f = fMAX = 1/tCYC
			5.0-ns cycle, 200 MHz		450	mA
			6.0-ns cycle, 167 MHz		400	mA
ISB1	Automatic CE	Max. VDD, Device Deselected,	4.0-ns cycle, 250MHz		200	mA
	Power Down	VIN ≥ VIH or VIN ≤ VIL,
			5.0-ns cycle, 200 MHz		200	mA
	Current—TTL Inputs	f = fMAX = 1/tCYC
			6.0-ns cycle, 167 MHz		200	mA
ISB2	Automatic CE	Max. VDD, Device Deselected,	All speed grades		120	mA
	Power Down	VIN ≤ 0.3V or
	Current—CMOS Inputs	VIN > VDDQ − 0.3V, f = 0

Notes

12.Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2). Undershoot: VIL(AC)> –2V (pulse width less than tCYC/2).

13.TPower-up: assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

14.The operation current is calculated with 50% read cycle and 50% write cycle.

Document #: 001-15032 Rev. *D Page 19 of 29

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