Cypress CY7C1472BV25 manual Pin Definitions Pin Name IO Type Pin Description, Adv/Ld, Dqpx, Tdi

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CY7C1470BV25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1472BV25, CY7C1474BV25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 1. Pin Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Name

IO Type

 

 

 

Pin Description

 

A0

Input-

 

Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the

 

A1

Synchronous

 

CLK.

 

 

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

a

Input-

 

Byte Write Select Inputs, Active LOW. Qualified with

 

to conduct writes to the SRAM. Sampled

 

BW

 

WE

 

BWb

Synchronous

 

on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls

 

BWc

 

 

DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf controls DQf and

 

BWd

 

 

DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.

 

BWe

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BWf

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BWg

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BWh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

 

Write Enable Input, Active LOW. Sampled on the rising edge of CLK if

 

is active LOW. This

 

WE

 

CEN

 

 

 

 

 

 

 

 

 

Synchronous

 

signal must be asserted LOW to initiate a write sequence.

 

 

 

 

 

 

 

 

 

Input-

 

Advance/Load Input Used to Advance the On-Chip Address Counter or Load a New Address.

 

ADV/LD

 

 

 

 

 

 

 

 

 

 

 

Synchronous

 

When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new

 

 

 

 

 

 

 

 

 

 

 

address can be loaded into the device for an access. After being deselected, ADV/LD must be driven

 

 

 

 

 

 

 

 

 

 

 

LOW to load a new address.

 

CLK

Input-

 

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with

 

CLK

 

 

CEN.

 

 

 

 

 

 

 

 

 

Clock

 

is only recognized if CEN is active LOW.

 

 

1

 

Input-

 

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with

 

CE

 

 

 

 

 

 

 

 

 

 

Synchronous

 

CE2 and CE3 to select/deselect the device.

 

CE2

Input-

 

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

 

 

 

 

 

 

 

 

 

Synchronous

 

CE1 and CE3 to select/deselect the device.

 

 

3

 

Input-

 

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with

 

CE

 

 

 

 

 

 

 

 

 

 

Synchronous

 

CE1 and CE2 to select/deselect the device.

 

 

 

 

 

Input-

 

Output Enable, Active LOW. Combined with the synchronous logic block inside the device to control

 

OE

 

 

 

 

 

 

 

 

 

 

Asynchronous

 

the direction of the IO pins. When LOW, the IO pins can behave as outputs. When deasserted HIGH,

 

 

 

 

 

 

 

 

 

 

 

IO pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write

 

 

 

 

 

 

 

 

 

 

 

sequence, during the first clock when emerging from a deselected state and when the device has

 

 

 

 

 

 

 

 

 

 

 

been deselected.

 

 

 

 

 

 

 

Input-

 

Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM.

 

CEN

 

 

 

 

 

 

 

 

 

 

Synchronous

 

When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the

 

 

 

 

 

 

 

 

 

 

 

device, CEN can be used to extend the previous cycle when required.

 

DQs

IO-

 

Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by

 

 

 

 

 

 

 

 

 

Synchronous

 

the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified

 

 

 

 

 

 

 

 

 

 

 

by A[18:0]

during the previous clock rise

of

the read cycle. The direction of the pins is controlled by

 

 

 

 

 

 

 

 

 

 

 

OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When

 

 

 

 

 

 

 

 

 

 

 

HIGH, DQa–DQhare placed in a tri-state condition. The outputs are automatically tri-stated during

 

 

 

 

 

 

 

 

 

 

 

the data portion of a write sequence, during the first clock when emerging from a deselected state, and

 

 

 

 

 

 

 

 

 

 

 

when the device is deselected, regardless of the state of OE.

 

DQPX

IO-

 

Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQ[71:0]. During write

 

 

 

 

 

 

 

 

 

Synchronous

 

sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and

 

 

 

 

 

 

 

 

 

 

 

DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, DQPg is controlled

 

 

 

 

 

 

 

 

 

 

 

by BWg, DQPh is controlled by BWh.

 

MODE

Input Strap Pin

 

Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.

 

 

 

 

 

 

 

 

 

 

 

Pulled LOW selects the linear burst order. MODE must not change states during operation. When

 

 

 

 

 

 

 

 

 

 

 

left floating MODE defaults HIGH, to an interleaved burst order.

 

TDO

JTAG Serial

 

Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK.

 

 

 

 

 

 

 

 

 

Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

 

 

 

 

 

 

 

 

 

 

 

 

 

TDI

JTAG Serial Input

 

Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.

 

 

 

 

 

 

 

 

 

Synchronous

 

 

 

 

 

 

 

 

 

 

 

 

Document #: 001-15032 Rev. *D

 

 

 

 

 

 

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Contents Description 250 MHz 200 MHz 167 MHz Unit FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1472BV25 4M x Logic Block Diagram CY7C1470BV25 2M xADV/LD Logic Block Diagram CY7C1474BV25 1M xPin Tqfp Pinout Pin ConfigurationsMode CENNC/1G CE2 CLK TDI TDOBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1474BV25 1M × TDI Pin Definitions Pin Name IO Type Pin DescriptionADV/LD DqpxFunctional Overview Burst Write Accesses ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Address Operation Truth TableUsed Function CY7C1474BV25 Partial Write Cycle DescriptionFunction CY7C1470BV25 Function CY7C1472BV25Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Instruction Set TAP Timing Parameter Description Min Max Unit Clock TAP AC Switching CharacteristicsHold Times Scan Register Sizes Register Name Bit Size TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions GND ≤ VI ≤ VddqBoundary Scan Exit Order 2M x Bit # Ball ID Identification Codes Instruction Description10 R1 11 R2 12 R3 13 P2 Boundary Scan Exit Order 4M xBoundary Scan Exit Order 1M x Bit # Ball IDRange Ambient Electrical CharacteristicsMaximum Ratings Operating RangeParameter Description Test Conditions Tqfp Fbga Unit CapacitanceThermal Resistance AC Test Loads and WaveformsOutput Times Switching CharacteristicsSetup Times Parameter Description 250 200 167 Unit Min MaxA3 A4 Switching WaveformsADV/LD Address DataNOP, Stall and Deselect Cycles Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. of Change Description of Change
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