Cypress CY7C1470BV25, CY7C1474BV25 Capacitance, Thermal Resistance, AC Test Loads and Waveforms

Page 20

CY7C1470BV25

CY7C1472BV25, CY7C1474BV25

Electrical Characteristics

Over the Operating Range[12, 13] (continued)

Parameter

Description

Test Conditions

Min

Max

Unit

ISB3

Automatic CE

Max. VDD, Device Deselected,

4.0-ns cycle, 250 MHz

 

200

mA

 

Power Down

VIN 0.3V or

 

 

 

 

 

5.0-ns cycle, 200 MHz

 

200

mA

 

Current—CMOS Inputs

VIN > VDDQ 0.3V,

 

 

 

 

 

 

 

 

 

 

 

f = fMAX = 1/tCYC

6.0-ns cycle, 167 MHz

 

200

mA

ISB4

Automatic CE

Max. VDD, Device Deselected,

All speed grades

 

135

mA

 

Power Down

VIN VIH or VIN VIL, f = 0

 

 

 

 

 

Current—TTL Inputs

 

 

 

 

 

Capacitance

Tested initially and after any design or process changes that may affect these parameters.

Parameter

Description

Test Conditions

100 TQFP

165 FBGA

209 FBGA

Unit

Max

Max

Max

 

 

 

 

CADDRESS

Address Input Capacitance

TA = 25°C, f = 1 MHz,

6

6

6

pF

 

 

VDD = 2.5V

 

 

 

 

CDATA

Data Input Capacitance

5

5

5

pF

 

 

VDDQ = 2.5V

 

 

 

 

CCTRL

Control Input Capacitance

8

8

8

pF

 

CCLK

Clock Input Capacitance

 

6

6

6

pF

CIO

Input/Output Capacitance

 

5

5

5

pF

Thermal Resistance

Tested initially and after any design or process changes that may affect these parameters.

Parameter

Description

Test Conditions

100 TQFP

165 FBGA

209 FBGA

Unit

Package

Package

Package

 

 

 

 

ΘJA

Thermal Resistance

Test conditions follow standard test

24.63

16.3

15.2

°C/W

 

(Junction to Ambient)

methods and procedures for

 

 

 

 

 

 

measuring thermal impedance, per

 

 

 

 

ΘJC

Thermal Resistance

2.28

2.1

1.7

°C/W

EIA/JESD51.

 

(Junction to Case)

 

 

 

 

 

AC Test Loads and Waveforms

2.5V IO Test Load

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

2.5V

 

 

 

 

 

 

R = 1667Ω

 

 

 

 

 

ALL INPUT PULSES

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDQ

 

 

 

 

 

 

 

 

 

 

Z0

= 50Ω

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RL = 50Ω

 

 

 

 

 

 

 

 

 

 

 

10%

 

 

 

 

 

 

90%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 pF

 

 

 

 

 

 

 

R = 1538Ω

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VL = 1.25V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

90%

10%

1 ns

 

INCLUDING

 

 

 

 

 

 

 

(c)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(a)

JIG AND

 

 

 

(b)

 

 

 

 

SCOPE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document #: 001-15032 Rev. *D

Page 20 of 29

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Contents Features Functional DescriptionSelection Guide Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1470BV25 2M x Logic Block Diagram CY7C1472BV25 4M xLogic Block Diagram CY7C1474BV25 1M x ADV/LDPin Configurations Pin Tqfp PinoutCEN NC/1G CE2 CLKTDI TDO ModeBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1474BV25 1M × Pin Definitions Pin Name IO Type Pin Description ADV/LDDqpx TDIFunctional Overview Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsBurst Write Accesses Used Truth TableAddress Operation Partial Write Cycle Description Function CY7C1470BV25Function CY7C1472BV25 Function CY7C1474BV25TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set TAP Timing Hold Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock TAP DC Electrical Characteristics And Operating Conditions 5V TAP AC Test ConditionsGND ≤ VI ≤ Vddq Scan Register Sizes Register Name Bit SizeIdentification Codes Instruction Description Boundary Scan Exit Order 2M x Bit # Ball IDBoundary Scan Exit Order 4M x Boundary Scan Exit Order 1M xBit # Ball ID 10 R1 11 R2 12 R3 13 P2Electrical Characteristics Maximum RatingsOperating Range Range AmbientCapacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Tqfp Fbga UnitSwitching Characteristics Setup TimesParameter Description 250 200 167 Unit Min Max Output TimesSwitching Waveforms ADV/LD AddressData A3 A4NOP, Stall and Deselect Cycles Ordering Information 250 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. of Change Description of Change Document History