Cypress CY7C1471V33, CY7C1475V33, CY7C1473V33 manual Truth Table, Address Operation, Used

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CY7C1471V33

CY7C1473V33

CY7C1475V33

Truth Table

The truth table for CY7C1471V33, CY7C1473V33, CY7C1475V33 follows.[2, 3, 4, 5, 6, 7, 8]

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operation

CE1

CE2

CE3

ZZ

ADV/LD

 

WE

 

 

BWX

 

OE

 

 

CEN

CLK

DQ

Used

 

 

 

 

 

 

 

Deselect Cycle

None

 

H

X

 

X

 

L

L

 

X

 

 

X

 

X

 

 

L

L->H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle

None

 

X

X

 

H

 

L

L

 

X

 

 

X

 

X

 

 

L

L->H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle

None

 

X

L

 

X

 

L

L

 

X

 

 

X

 

X

 

 

L

L->H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Continue Deselect Cycle

None

 

X

X

 

X

 

L

H

 

X

 

 

X

 

X

 

 

L

L->H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle

External

 

L

H

 

L

 

L

L

 

H

 

 

X

 

L

 

 

L

L->H

Data Out (Q)

(Begin Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle

Next

 

X

X

 

X

 

L

H

 

X

 

 

X

 

L

 

 

L

L->H

Data Out (Q)

(Continue Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOP/Dummy Read

External

 

L

H

 

L

 

L

L

 

H

 

 

X

 

H

 

 

L

L->H

Tri-State

(Begin Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dummy Read

Next

 

X

X

 

X

 

L

H

 

X

 

 

X

 

H

 

 

L

L->H

Tri-State

(Continue Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle

External

 

L

H

 

L

 

L

L

 

L

 

 

L

 

X

 

 

L

L->H

Data In (D)

(Begin Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle

Next

 

X

X

 

X

 

L

H

 

X

 

 

L

 

X

 

 

L

L->H

Data In (D)

(Continue Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOP/Write Abort

None

 

L

H

 

L

 

L

L

 

L

 

 

H

 

X

 

 

L

L->H

Tri-State

(Begin Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Abort

Next

 

X

X

 

X

 

L

H

 

X

 

 

H

 

X

 

 

L

L->H

Tri-State

(Continue Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ignore Clock Edge (Stall)

Current

 

X

X

 

X

 

L

X

 

X

 

 

X

 

X

 

 

H

L->H

-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sleep Mode

None

 

X

X

 

X

 

H

X

 

X

 

 

X

 

X

 

 

X

X

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

2.X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = L signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired Byte Write Selects are asserted, see “Truth Table for Read/Write” on page 12 for details.

3.Write is defined by BWX, and WE. See “Truth Table for Read/Write” on page 12.

4.When a Write cycle is detected, all IOs are tri-stated, even during Byte Writes.

5.The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

6.CEN = H, inserts wait states.

7.Device powers up deselected with the IOs in a tri-state condition, regardless of OE.

8.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tri-state when OE is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.

Document #: 38-05288 Rev. *J

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Contents 133 MHz 117 MHz Unit FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1473V33 4M x Logic Block Diagram CY7C1471V33 2M xLogic Block Diagram CY7C1475V33 1M x CY7C1471V33 Pin Configurations Pin Tqfp PinoutCY7C1473V33 CY7C1473V33 4M x ADV/LD Pin Definitions Functional Overview Single Read AccessesBurst Read Accesses Single Write AccessesZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Used Truth TableAddress Operation Function BW b BW a Truth Table for Read/WriteFunction Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set TAP RegistersBypass TAP TimingHold Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Output TimesParameter Description Test Conditions Min TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsIdentification Codes Identification Register DefinitionsScan Register Sizes Bit # Ball ID Boundary Scan Exit Order 2M xBoundary Scan Exit Order 4M x V10 Boundary Scan Exit Order 1M xP10 W10Range Ambient Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Loads and Waveforms CapacitanceThermal Resistance Description 133 MHz 117 MHz Unit Parameter Min Max Switching CharacteristicsSetup Times Read Switching WaveformsRite Stall NOP AddressQA2 StallDON’T Care Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History Issue Orig. of Change Description of Change DateVKN/AESA VKN
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