Cypress CY7C1475V33, CY7C1473V33, CY7C1471V33 Truth Table for Read/Write, Function BW b BW a

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CY7C1471V33

CY7C1473V33

CY7C1475V33

Truth Table for Read/Write

The read-write truth table for CY7C1471V33 follows.[2, 3, 9]

Function

WE

BW

A

BW

B

BW

C

BW

D

Read

H

X

X

X

X

Write No bytes written

L

H

H

H

H

Write Byte A – (DQA and DQPA)

L

L

H

H

H

Write Byte B – (DQB and DQPB)

L

H

L

H

H

Write Byte C – (DQC and DQPC)

L

H

H

L

H

Write Byte D – (DQD and DQPD)

L

H

H

H

L

Write All Bytes

L

L

L

L

L

Truth Table for Read/Write

The read-write truth table for CY7C1473V33 follows.[2, 3, 9]

Function
Function		WE			BWb			BWa
Read		H			X			X

Write – No Bytes Written		L			H			H

Write Byte a – (DQa and DQPa)		L			H			L
Write Byte b – (DQb and DQPb)		L			L			H
Write Both Bytes		L			L			L

Truth Table for Read/Write

The read-write truth table for CY7C1475V33 follows.[2, 3, 9]

Function							x
Function		WE			BW		x
Read		H				X

Write – No Bytes Written		L				H

Write Byte X − (DQx and DQPx)		L				L
Write All Bytes		L		All				= L
Write All Bytes		L		All		BW		= L

Note

9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is based on which byte write is active.

Document #: 38-05288 Rev. *J

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Contents Features Functional DescriptionSelection Guide 133 MHz 117 MHz UnitLogic Block Diagram CY7C1471V33 2M x Logic Block Diagram CY7C1473V33 4M xLogic Block Diagram CY7C1475V33 1M x Pin Configurations Pin Tqfp Pinout CY7C1471V33CY7C1473V33 CY7C1473V33 4M x ADV/LD Pin Definitions Single Read Accesses Burst Read AccessesSingle Write Accesses Functional OverviewInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Truth Table Address OperationUsed Truth Table for Read/Write FunctionFunction BW b BW a TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Registers TAP Instruction SetTAP Timing BypassTAP AC Switching Characteristics Parameter Description Min Max Unit ClockOutput Times Hold TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Parameter Description Test Conditions MinIdentification Register Definitions Scan Register SizesIdentification Codes Boundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID Boundary Scan Exit Order 1M x P10W10 V10Electrical Characteristics Maximum RatingsOperating Range Range AmbientCapacitance Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Setup TimesDescription 133 MHz 117 MHz Unit Parameter Min Max Switching Waveforms RiteRead Address QA2Stall Stall NOPDON’T Care Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Issue Orig. of Change Description of Change Date Document HistoryVKN VKN/AESA