Cypress CY7C1475V33, CY7C1473V33, CY7C1471V33 manual Switching Waveforms, Rite, Read

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CY7C1471V33

CY7C1473V33

CY7C1475V33

Switching Waveforms

Figure 1 shows read-write timing waveform.[20, 21, 22]

 

 

 

Figure 1. Read/Write Timing

 

 

 

 

1

2

tCYC 3

4

5

6

7

8

9

10

CLK

 

 

 

 

 

 

 

 

 

tCENS tCENH

tCH

tCL

 

 

 

 

 

 

 

CEN

tCES tCEH

CE

ADV/LD

W E

BW X

ADDRESS A1 A2

 

tAS tAH

 

DQ

 

D(A1)

 

tDS

tDH

OE

 

 

COM M AND

W RITE

W RITE

 

 

D(A1)

D(A2)

 

A3

A4

 

 

A5

A6

A7

 

 

tCDV

 

 

 

 

 

 

 

 

tCLZ

tDOH

tOEV

tCHZ

 

 

 

D(A2)

D(A2+1)

Q(A3)

Q(A4)

 

Q(A4+1)

D(A5)

Q(A6)

D(A7)

 

 

 

tOEHZ

 

tDOH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tOELZ

 

 

 

BURST

READ

READ

BURST

 

W RITE

READ

W RITE

DESELECT

W RITE

Q(A3)

Q(A4)

READ

 

D(A5)

Q(A6)

D(A7)

 

D(A2+1)

 

 

Q(A4+1)

 

 

 

 

 

DON’T CARE

UNDEFINED

Notes

20.For this waveform ZZ is tied LOW.

21.When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH.

22.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.

Document #: 38-05288 Rev. *J

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Contents Features Functional DescriptionSelection Guide 133 MHz 117 MHz UnitLogic Block Diagram CY7C1471V33 2M x Logic Block Diagram CY7C1473V33 4M xLogic Block Diagram CY7C1475V33 1M x Pin Configurations Pin Tqfp Pinout CY7C1471V33CY7C1473V33 CY7C1473V33 4M x ADV/LD Pin Definitions Single Read Accesses Burst Read AccessesSingle Write Accesses Functional OverviewInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Truth Table Address OperationUsed Truth Table for Read/Write FunctionFunction BW b BW a TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Registers TAP Instruction SetTAP Timing BypassTAP AC Switching Characteristics Parameter Description Min Max Unit ClockOutput Times Hold TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Parameter Description Test Conditions MinIdentification Register Definitions Scan Register SizesIdentification Codes Boundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID Boundary Scan Exit Order 1M x P10W10 V10 Electrical Characteristics Maximum Ratings Operating Range Range AmbientCapacitance Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Setup TimesDescription 133 MHz 117 MHz Unit Parameter Min Max Switching Waveforms RiteRead Address QA2Stall Stall NOPDON’T Care Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Issue Orig. of Change Description of Change Date Document HistoryVKN VKN/AESA