Cypress CY7C1473V33 manual Document History, Issue Orig. of Change Description of Change Date

Page 31

CY7C1471V33

CY7C1473V33

CY7C1475V33

Document History Page

Document Title: CY7C1471V33/CY7C1473V33/CY7C1475V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture

Document Number: 38-05288

REV.

ECN NO.

Issue

Orig. of Change

Description of Change

Date

 

 

 

 

 

 

 

 

 

**

114675

08/06/02

PKS

New Data Sheet

 

 

 

 

 

*A

121521

02/07/03

CJM

Updated features for package offering

 

 

 

 

Updated ordering information

 

 

 

 

Changed Advanced Information to Preliminary

*B

223721

See ECN

NJY

Changed timing diagrams

 

 

 

 

Changed logic block diagrams

 

 

 

 

Modified Functional Description

 

 

 

 

Modified “Functional Overview” section

 

 

 

 

Added boundary scan order for all packages

 

 

 

 

Included thermal numbers and capacitance values for all packages

 

 

 

 

Removed 150-MHz speed grade offering

 

 

 

 

Included ISB and IDD values

 

 

 

 

Changed package outline for 165FBGA package and 209-Ball BGA package

 

 

 

 

Removed 119-BGA package offering

*C

235012

See ECN

RYQ

Minor Change: The data sheets do not match on the spec system and

 

 

 

 

external web

*D

243572

See ECN

NJY

Changed ball H2 from VDD to NC in the 165-Ball FBGA package in page 6

 

 

 

 

Modified capacitance values on page 21

*E

299511

See ECN

SYT

Removed 117-MHz Speed Bin

 

 

 

 

Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for 100

 

 

 

 

TQFP Package on Page # 21

 

 

 

 

Added Pb-free information for 100-Pin TQFP, 165 FBGA and 209 BGA

 

 

 

 

Packages

 

 

 

 

Added comment of ‘Pb-free BG packages availability’ below the Ordering

 

 

 

 

Information

*F

320197

See ECN

PCI

Corrected part number typos in the logic block diagram on page# 2

 

 

 

 

 

*G

331513

See ECN

PCI

Address expansion pins/balls in the pinouts for all packages are modified as

 

 

 

 

per JEDEC standard

 

 

 

 

Added Address Expansion pins in the Pin Definitions Table

 

 

 

 

Added Industrial Operating Range

 

 

 

 

Modified VOL, VOH Test Conditions

 

 

 

 

Updated Ordering Information Table

*H

416221

See ECN

RXU

Converted from Preliminary to Final

 

 

 

 

Changed address of Cypress Semiconductor Corporation on Page# 1 from

 

 

 

 

“3901 North First Street” to “198 Champion Court”

 

 

 

 

Removed 100MHz Speed bin & Added 117MHz Speed bin

 

 

 

 

Changed the description of IX from Input Load Current to Input Leakage

 

 

 

 

Current on page# 19

 

 

 

 

Changed the IX current values of MODE on page # 19 from –5 A and 30 A

 

 

 

 

to –30 A and 5 A

 

 

 

 

Changed the IX current values of ZZ on page # 19 from –30 A and 5 A

 

 

 

 

to –5 A and 30 A

 

 

 

 

Changed VIH < VDD to VIH < VDD on page # 19

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

Information table

 

 

 

 

Updated the Ordering Information Table

Document #: 38-05288 Rev. *J

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Image 31
Contents 133 MHz 117 MHz Unit FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1473V33 4M x Logic Block Diagram CY7C1471V33 2M xLogic Block Diagram CY7C1475V33 1M x CY7C1471V33 Pin Configurations Pin Tqfp PinoutCY7C1473V33 CY7C1473V33 4M x ADV/LD Pin Definitions Functional Overview Single Read AccessesBurst Read Accesses Single Write AccessesLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Address Operation Truth TableUsed Function Truth Table for Read/WriteFunction BW b BW a TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set TAP RegistersBypass TAP TimingHold Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Output TimesParameter Description Test Conditions Min TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsScan Register Sizes Identification Register DefinitionsIdentification Codes Boundary Scan Exit Order 4M x Boundary Scan Exit Order 2M xBit # Ball ID V10 Boundary Scan Exit Order 1M xP10 W10Range Ambient Electrical CharacteristicsMaximum Ratings Operating RangeThermal Resistance CapacitanceAC Test Loads and Waveforms Setup Times Switching CharacteristicsDescription 133 MHz 117 MHz Unit Parameter Min Max Rite Switching WaveformsRead Stall NOP AddressQA2 StallDON’T Care Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History Issue Orig. of Change Description of Change DateVKN/AESA VKN