Cypress CY7C1471V33, CY7C1475V33, CY7C1473V33 manual Boundary Scan Exit Order 1M x, P10, W10, V10

Page 20

CY7C1471V33

CY7C1473V33

CY7C1475V33

Boundary Scan Exit Order (1M x 72)

Bit #

209-Ball ID

 

Bit #

209-Ball ID

 

Bit #

209-Ball ID

 

Bit #

209-Ball ID

1

A1

 

29

T1

 

57

U10

 

85

B11

 

 

 

 

 

 

 

 

 

 

 

2

A2

 

30

T2

 

58

T11

 

86

B10

 

 

 

 

 

 

 

 

 

 

 

3

B1

 

31

U1

 

59

T10

 

87

A11

 

 

 

 

 

 

 

 

 

 

 

4

B2

 

32

U2

 

60

R11

 

88

A10

 

 

 

 

 

 

 

 

 

 

 

5

C1

 

33

V1

 

61

R10

 

89

A7

 

 

 

 

 

 

 

 

 

 

 

6

C2

 

34

V2

 

62

P11

 

90

A5

 

 

 

 

 

 

 

 

 

 

 

7

D1

 

35

W1

 

63

P10

 

91

A9

 

 

 

 

 

 

 

 

 

 

 

8

D2

 

36

W2

 

64

N11

 

92

U8

 

 

 

 

 

 

 

 

 

 

 

9

E1

 

37

T6

 

65

N10

 

93

A6

 

 

 

 

 

 

 

 

 

 

 

10

E2

 

38

V3

 

66

M11

 

94

D6

 

 

 

 

 

 

 

 

 

 

 

11

F1

 

39

V4

 

67

M10

 

95

K6

 

 

 

 

 

 

 

 

 

 

 

12

F2

 

40

U4

 

68

L11

 

96

B6

 

 

 

 

 

 

 

 

 

 

 

13

G1

 

41

W5

 

69

L10

 

97

K3

 

 

 

 

 

 

 

 

 

 

 

14

G2

 

42

V6

 

70

P6

 

98

A8

 

 

 

 

 

 

 

 

 

 

 

15

H1

 

43

W6

 

71

J11

 

99

B4

 

 

 

 

 

 

 

 

 

 

 

16

H2

 

44

V5

 

72

J10

 

100

B3

 

 

 

 

 

 

 

 

 

 

 

17

J1

 

45

U5

 

73

H11

 

101

C3

 

 

 

 

 

 

 

 

 

 

 

18

J2

 

46

U6

 

74

H10

 

102

C4

 

 

 

 

 

 

 

 

 

 

 

19

L1

 

47

W7

 

75

G11

 

103

C8

 

 

 

 

 

 

 

 

 

 

 

20

L2

 

48

V7

 

76

G10

 

104

C9

 

 

 

 

 

 

 

 

 

 

 

21

M1

 

49

U7

 

77

F11

 

105

B9

 

 

 

 

 

 

 

 

 

 

 

22

M2

 

50

V8

 

78

F10

 

106

B8

 

 

 

 

 

 

 

 

 

 

 

23

N1

 

51

V9

 

79

E10

 

107

A4

 

 

 

 

 

 

 

 

 

 

 

24

N2

 

52

W11

 

80

E11

 

108

C6

 

 

 

 

 

 

 

 

 

 

 

25

P1

 

53

W10

 

81

D11

 

109

B7

 

 

 

 

 

 

 

 

 

 

 

26

P2

 

54

V11

 

82

D10

 

110

A3

 

 

 

 

 

 

 

 

 

 

 

27

R2

 

55

V10

 

83

C11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

28

R1

 

56

U11

 

84

C10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document #: 38-05288 Rev. *J

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Contents Features Functional DescriptionSelection Guide 133 MHz 117 MHz UnitLogic Block Diagram CY7C1471V33 2M x Logic Block Diagram CY7C1473V33 4M xLogic Block Diagram CY7C1475V33 1M x Pin Configurations Pin Tqfp Pinout CY7C1471V33CY7C1473V33 CY7C1473V33 4M x ADV/LD Pin Definitions Single Read Accesses Burst Read AccessesSingle Write Accesses Functional OverviewZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Used Truth TableAddress Operation Function BW b BW a Truth Table for Read/WriteFunction Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Registers TAP Instruction SetTAP Timing BypassTAP AC Switching Characteristics Parameter Description Min Max Unit ClockOutput Times Hold TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Parameter Description Test Conditions MinIdentification Codes Identification Register DefinitionsScan Register Sizes Bit # Ball ID Boundary Scan Exit Order 2M xBoundary Scan Exit Order 4M x Boundary Scan Exit Order 1M x P10W10 V10Electrical Characteristics Maximum RatingsOperating Range Range AmbientAC Test Loads and Waveforms CapacitanceThermal Resistance Description 133 MHz 117 MHz Unit Parameter Min Max Switching CharacteristicsSetup Times Read Switching WaveformsRite Address QA2Stall Stall NOPDON’T Care Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Issue Orig. of Change Description of Change Date Document HistoryVKN VKN/AESA