Cypress CY7C1475V33, CY7C1471V33 manual CY7C1473V33 4M x

Page 6

CY7C1471V33

CY7C1473V33

CY7C1475V33

Pin Configurations (continued)

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1471V33 (2M x 36)

1

2

3

4

5

6

7

8

9

10

11

A

NC/576M

1

C

B

3

A

CE

BW

BW

CE

CEN

ADV/LD

A

A

NC

B

NC/1G

A

CE2

D

A

CLK

A

A

NC

BW

BW

WE

OE

C

DQPC

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC

DQPB

D

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

E

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

F

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

G

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

H

NC

NC

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

ZZ

J

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

K

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

L

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

M

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

N

DQPD

NC

VDDQ

VSS

NC

NC

NC

VSS

VDDQ

NC

DQPA

P

NC/144M

A

A

A

TDI

A1

TDO

A

A

A

NC/288M

R

MODE

A

A

A

TMS

A0

TCK

A

A

A

A

CY7C1473V33 (4M x 18)

1

2

3

4

5

6

7

8

9

10

11

A

NC/576M

1

B

NC

3

A

CE

BW

CE

CEN

ADV/LD

A

A

A

B

NC/1G

A

CE2

NC

A

CLK

A

A

NC

BW

WE

OE

C

NC

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC

DQPA

D

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

E

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

F

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

G

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

H

NC

NC

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

ZZ

J

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

K

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

L

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

M

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

N

DQPB

NC

VDDQ

VSS

NC

NC

NC

VSS

VDDQ

NC

NC

P

NC/144M

A

A

A

TDI

A1

TDO

A

A

A

NC/288M

R

MODE

A

A

A

TMS

A0

TCK

A

A

A

A

Document #: 38-05288 Rev. *J

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Contents Selection Guide FeaturesFunctional Description 133 MHz 117 MHz UnitLogic Block Diagram CY7C1471V33 2M x Logic Block Diagram CY7C1473V33 4M xLogic Block Diagram CY7C1475V33 1M x Pin Configurations Pin Tqfp Pinout CY7C1471V33CY7C1473V33 CY7C1473V33 4M x ADV/LD Pin Definitions Single Write Accesses Single Read AccessesBurst Read Accesses Functional OverviewInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Truth Table Address OperationUsed Truth Table for Read/Write FunctionFunction BW b BW a TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Registers TAP Instruction SetTAP Timing BypassOutput Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Hold Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Parameter Description Test Conditions MinIdentification Register Definitions Scan Register SizesIdentification Codes Boundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID W10 Boundary Scan Exit Order 1M xP10 V10Operating Range Electrical CharacteristicsMaximum Ratings Range AmbientCapacitance Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Setup TimesDescription 133 MHz 117 MHz Unit Parameter Min Max Switching Waveforms RiteRead Stall AddressQA2 Stall NOPDON’T Care Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Issue Orig. of Change Description of Change Date Document HistoryVKN VKN/AESA