Cypress CY7C1424BV18, CY7C1423BV18, CY7C1429BV18, CY7C1422BV18 manual TAP Controller State Diagram

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CY7C1422BV18, CY7C1429BV18

CY7C1423BV18, CY7C1424BV18

TAP Controller State Diagram

The state diagram for the TAP controller follows. [9]

1

0

TEST-LOGIC RESET

0

TEST-LOGIC/ IDLE

1

 

1

1

SELECT

SELECT

 

DR-SCAN

 

IR-SCAN

 

0

 

0

 

1

 

1

CAPTURE-DR

 

CAPTURE-IR

 

0

 

0

 

SHIFT-DR

0

SHIFT-IR

0

1

 

1

 

EXIT1-DR

1

EXIT1-IR

1

 

 

0

 

0

 

PAUSE-DR

0

PAUSE-IR

0

1

 

1

 

0

 

0

 

EXIT2-DR

 

EXIT2-IR

 

1

 

1

 

UPDATE-DR

 

UPDATE-IR

 

1

 

1

 

0

 

0

 

Note

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document #: 001-07035 Rev. *D

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Contents Functional Description FeaturesConfigurations Selection GuideDoff Logic Block Diagram CY7C1422BV18CLK Logic Block Diagram CY7C1423BV18 Logic Block Diagram CY7C1424BV18CY7C1422BV18 4M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1429BV18 4M xCY7C1423BV18 2M x CY7C1424BV18 1M xSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Referenced with Respect to Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Application Example Echo ClocksLD R/W Truth TableWrite Cycle Descriptions BWS0/ BWS1 NWS0 NWS1BWS0 BWS0 BWS1 BWS2 BWS3Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TDI TAP Controller Block DiagramTAP Electrical Characteristics TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga UnitLOW Switching CharacteristicsHigh Static to DLL Reset DLL TimingBurst Switching WaveformsNOP Read Write Ordering Information 250 167 Package Diagram Ball Fbga 15 x 17 x 1.4 mmDocument History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions REV ECN no Submission ORIG. Description of Change Date