Cypress CY7C1429BV18, CY7C1423BV18, CY7C1424BV18, CY7C1422BV18 manual AC Electrical Characteristics

Page 21

CY7C1422BV18, CY7C1429BV18

CY7C1423BV18, CY7C1424BV18

Electrical Characteristics (continued)

DC Electrical Characteristics

Over the Operating Range [12]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

IDD	VDD Operating Supply	VDD = Max,	200MHz	(x8)			600	mA
		IOUT = 0 mA,
		IOUT = 0 mA,		(x9)			600
		f = fMAX = 1/tCYC
		f = fMAX = 1/tCYC		(x18)			600
				(x18)			600

				(x36)			665

			167MHz	(x8)			500	mA

				(x9)			500

				(x18)			500

				(x36)			560

ISB1	Automatic Power down	Max VDD,	300MHz	(x8)			325	mA
	Current	Both Ports Deselected,
	Current	Both Ports Deselected,		(x9)			325
		VIN ≥ VIH or VIN ≤ VIL		(x9)			325


		f = fMAX = 1/tCYC,		(x18)			345
		Inputs Static
		Inputs Static		(x36)			375
				(x36)			375

			278MHz	(x8)			310	mA

				(x9)			310

				(x18)			325

				(x36)			355

			250MHz	(x8)			300	mA

				(x9)			300

				(x18)			310

				(x36)			330

			200MHz	(x8)			285	mA

				(x9)			285

				(x18)			290

				(x36)			300

			167MHz	(x8)			275	mA

				(x9)			275

				(x18)			275

				(x36)			285

AC Electrical Characteristics

Over the Operating Range [11]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

VIH

VIL

Input HIGH Voltage		VREF + 0.2	–	–	V
Input LOW Voltage		–	–	VREF – 0.2	V

Document #: 001-07035 Rev. *D

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1422BV18 CLKDoff Logic Block Diagram CY7C1424BV18 Logic Block Diagram CY7C1423BV18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1422BV18 4M x CY7C1429BV18 4M xCY7C1424BV18 1M x CY7C1423BV18 2M xPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Echo Clocks Application ExampleWrite Cycle Descriptions Truth TableLD R/W BWS0/ BWS1 NWS0 NWS1BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence in DDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitSwitching Characteristics HighLOW DLL Timing Static to DLL ResetSwitching Waveforms NOP Read WriteBurst Ordering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History REV ECN no Submission ORIG. Description of Change Date