Cypress CY7C1424BV18, CY7C1423BV18, CY7C1429BV18 manual Logic Block Diagram CY7C1422BV18, Clk, Doff

CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

Logic Block Diagram (CY7C1422BV18)
	D[7:0]	8
				Write	Write
	21	Address		Data Reg	Data Reg
A(20:0)			Decode			Decode
		Register		2M x	2M x
									LD
	K	Gen.	WriteAdd.	8Array	8Array	ReadAdd.
							Control		C
	K	CLK					Logic
DOFF				Read Data Reg.					C
R/W				16	8
						Reg.	Reg.
V								8
	REF	Control
					8
	LD	Logic				Reg.		8	8
NWS[1:0]

CQ

CQ

Q[7:0]

Logic Block Diagram (CY7C1429BV18)
	D[8:0]	9
				Write	Write
	21	Address		Data Reg	Data Reg
A(20:0)			Decode			Decode
		Register		2M x	2M x
									LD
	K	Gen.	WriteAdd.	9Array	9Array	ReadAdd.
							Control		C
	K	CLK					Logic
DOFF				Read Data Reg.					C
R/W				18	9
						Reg.	Reg.
V								9
	REF	Control
					9
	LD	Logic				Reg.		9	9
BWS[0]

CQ

CQ

Q[8:0]

Document #: 001-07035 Rev. *D Page 2 of 30

[+] Feedback