
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
Features
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■300 MHz clock for high bandwidth
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■Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) at 300 MHz
■Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only
■Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
■Echo clocks (CQ and CQ) simplify data capture in
■Synchronous internally
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■Operates similar to a
■1.8V core power supply with HSTL inputs and outputs
■Variable drive HSTL output buffers
■Expanded HSTL output voltage
■Available in
■Offered in both
■JTAG 1149.1 compatible test access port
■Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1422BV18 – 4M x 8
CY7C1429BV18 – 4M x 9
CY7C1423BV18 – 2M x 18
CY7C1424BV18 – 1M x 36
Functional Description
The CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and CY7C1424BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO
Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual
All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with
Selection Guide
Description
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency |
| 300 | 278 | 250 | 200 | 167 | MHz |
Maximum Operating Current | x8 | 825 | 775 | 700 | 600 | 500 | mA |
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| x9 | 845 | 775 | 700 | 600 | 500 |
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| x18 | 880 | 815 | 740 | 600 | 500 |
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| x36 | 980 | 890 | 800 | 665 | 560 |
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Cypress Semiconductor Corporation • 198 Champion Court | • | San Jose, CA | • | |
Document #: |
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| Revised June 16, 2008 |
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