Cypress CY7C1429BV18 manual Features, Configurations, Functional Description, Selection Guide

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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

Features

36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)

300 MHz clock for high bandwidth

2-word burst for reducing address bus frequency

Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz

Two input clocks (K and K) for precise DDR timing SRAM uses rising edges only

Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches

Echo clocks (CQ and CQ) simplify data capture in high-speed systems

Synchronous internally self-timed writes

DDR-II operates with 1.5 cycle read latency when the DLL is enabled

Operates similar to a DDR-I device with 1 cycle read latency in DLL off mode

1.8V core power supply with HSTL inputs and outputs

Variable drive HSTL output buffers

Expanded HSTL output voltage (1.4V–VDD)

Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

Offered in both Pb-free and non Pb-free packages

JTAG 1149.1 compatible test access port

Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1422BV18 – 4M x 8

CY7C1429BV18 – 4M x 9

CY7C1423BV18 – 2M x 18

CY7C1424BV18 – 1M x 36

Functional Description

The CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and CY7C1424BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO (DDR-II SIO) architecture. The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1422BV18, two 9-bit words in the case of CY7C1429BV18, two 18-bit words in the case of CY7C1423BV18, and two 36-bit words in the case of CY7C1424BV18 that burst sequentially into or out of the device.

Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual DDR-II SIO SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Description

300 MHz

278 MHz

250 MHz

200 MHz

167 MHz

Unit

Maximum Operating Frequency

 

300

278

250

200

167

MHz

Maximum Operating Current

x8

825

775

700

600

500

mA

 

 

 

 

 

 

 

 

 

x9

845

775

700

600

500

 

 

 

 

 

 

 

 

 

 

x18

880

815

740

600

500

 

 

 

 

 

 

 

 

 

 

x36

980

890

800

665

560

 

 

 

 

 

 

 

 

 

Cypress Semiconductor Corporation • 198 Champion Court

San Jose, CA 95134-1709

408-943-2600

Document #: 001-07035 Rev. *D

 

 

Revised June 16, 2008

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Contents Configurations FeaturesFunctional Description Selection GuideCLK Logic Block Diagram CY7C1422BV18Doff Logic Block Diagram CY7C1424BV18 Logic Block Diagram CY7C1423BV18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1422BV18 4M x CY7C1429BV18 4M xCY7C1424BV18 1M x CY7C1423BV18 2M xPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Echo Clocks Application ExampleWrite Cycle Descriptions Truth TableLD R/W BWS0/ BWS1 NWS0 NWS1BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in DDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitHigh Switching CharacteristicsLOW DLL Timing Static to DLL ResetNOP Read Write Switching WaveformsBurst Ordering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History REV ECN no Submission ORIG. Description of Change Date